xref: /OK3568_Linux_fs/u-boot/drivers/usb/host/sl811.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun #ifndef __UBOOT_SL811_H
2*4882a593Smuzhiyun #define __UBOOT_SL811_H
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #undef SL811_DEBUG
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifdef SL811_DEBUG
7*4882a593Smuzhiyun 	#define PDEBUG(level, fmt, args...) \
8*4882a593Smuzhiyun 		if (debug >= (level)) printf("[%s:%d] " fmt, \
9*4882a593Smuzhiyun 		__PRETTY_FUNCTION__, __LINE__ , ## args)
10*4882a593Smuzhiyun #else
11*4882a593Smuzhiyun 	#define PDEBUG(level, fmt, args...) do {} while(0)
12*4882a593Smuzhiyun #endif
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* Sl811 host control register */
15*4882a593Smuzhiyun #define	SL811_CTRL_A		0x00
16*4882a593Smuzhiyun #define	SL811_ADDR_A		0x01
17*4882a593Smuzhiyun #define	SL811_LEN_A		0x02
18*4882a593Smuzhiyun #define	SL811_STS_A		0x03	/* read	*/
19*4882a593Smuzhiyun #define	SL811_PIDEP_A		0x03	/* write */
20*4882a593Smuzhiyun #define	SL811_CNT_A		0x04	/* read	*/
21*4882a593Smuzhiyun #define	SL811_DEV_A		0x04	/* write */
22*4882a593Smuzhiyun #define	SL811_CTRL1		0x05
23*4882a593Smuzhiyun #define	SL811_INTR		0x06
24*4882a593Smuzhiyun #define	SL811_CTRL_B		0x08
25*4882a593Smuzhiyun #define	SL811_ADDR_B		0x09
26*4882a593Smuzhiyun #define	SL811_LEN_B		0x0A
27*4882a593Smuzhiyun #define	SL811_STS_B		0x0B	/* read	*/
28*4882a593Smuzhiyun #define	SL811_PIDEP_B		0x0B	/* write */
29*4882a593Smuzhiyun #define	SL811_CNT_B		0x0C	/* read	*/
30*4882a593Smuzhiyun #define	SL811_DEV_B		0x0C	/* write */
31*4882a593Smuzhiyun #define	SL811_INTRSTS		0x0D	/* write clears	bitwise	*/
32*4882a593Smuzhiyun #define	SL811_HWREV		0x0E	/* read	*/
33*4882a593Smuzhiyun #define	SL811_SOFLOW		0x0E	/* write */
34*4882a593Smuzhiyun #define	SL811_SOFCNTDIV		0x0F	/* read	*/
35*4882a593Smuzhiyun #define	SL811_CTRL2		0x0F	/* write */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* USB control register bits (addr 0x00 and addr 0x08) */
38*4882a593Smuzhiyun #define	SL811_USB_CTRL_ARM	0x01
39*4882a593Smuzhiyun #define	SL811_USB_CTRL_ENABLE	0x02
40*4882a593Smuzhiyun #define	SL811_USB_CTRL_DIR_OUT	0x04
41*4882a593Smuzhiyun #define	SL811_USB_CTRL_ISO	0x10
42*4882a593Smuzhiyun #define	SL811_USB_CTRL_SOF	0x20
43*4882a593Smuzhiyun #define	SL811_USB_CTRL_TOGGLE_1	0x40
44*4882a593Smuzhiyun #define	SL811_USB_CTRL_PREAMBLE	0x80
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* USB status register bits (addr 0x03 and addr 0x0B) */
47*4882a593Smuzhiyun #define	SL811_USB_STS_ACK	0x01
48*4882a593Smuzhiyun #define	SL811_USB_STS_ERROR	0x02
49*4882a593Smuzhiyun #define	SL811_USB_STS_TIMEOUT	0x04
50*4882a593Smuzhiyun #define	SL811_USB_STS_TOGGLE_1	0x08
51*4882a593Smuzhiyun #define	SL811_USB_STS_SETUP	0x10
52*4882a593Smuzhiyun #define	SL811_USB_STS_OVERFLOW	0x20
53*4882a593Smuzhiyun #define	SL811_USB_STS_NAK	0x40
54*4882a593Smuzhiyun #define	SL811_USB_STS_STALL	0x80
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* Control register 1 bits (addr 0x05) */
57*4882a593Smuzhiyun #define	SL811_CTRL1_SOF		0x01
58*4882a593Smuzhiyun #define	SL811_CTRL1_RESET	0x08
59*4882a593Smuzhiyun #define	SL811_CTRL1_JKSTATE	0x10
60*4882a593Smuzhiyun #define	SL811_CTRL1_SPEED_LOW	0x20
61*4882a593Smuzhiyun #define	SL811_CTRL1_SUSPEND	0x40
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */
64*4882a593Smuzhiyun #define	SL811_INTR_DONE_A	0x01
65*4882a593Smuzhiyun #define	SL811_INTR_DONE_B	0x02
66*4882a593Smuzhiyun #define	SL811_INTR_SOF		0x10
67*4882a593Smuzhiyun #define	SL811_INTR_INSRMV	0x20
68*4882a593Smuzhiyun #define	SL811_INTR_DETECT	0x40
69*4882a593Smuzhiyun #define	SL811_INTR_NOTPRESENT	0x40
70*4882a593Smuzhiyun #define	SL811_INTR_SPEED_FULL	0x80    /* only in status reg */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* HW rev and SOF lo register bits (addr 0x0E) */
73*4882a593Smuzhiyun #define	SL811_HWR_HWREV		0xF0
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* SOF counter and control reg 2 (addr 0x0F) */
76*4882a593Smuzhiyun #define	SL811_CTL2_SOFHI	0x3F
77*4882a593Smuzhiyun #define	SL811_CTL2_DSWAP	0x40
78*4882a593Smuzhiyun #define	SL811_CTL2_HOST		0x80
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* Set up for 1-ms SOF time. */
81*4882a593Smuzhiyun #define SL811_12M_LOW		0xE0
82*4882a593Smuzhiyun #define SL811_12M_HI		0x2E
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define SL811_DATA_START	0x10
85*4882a593Smuzhiyun #define SL811_DATA_LIMIT	240
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* Requests: bRequest << 8 | bmRequestType */
88*4882a593Smuzhiyun #define RH_GET_STATUS           0x0080
89*4882a593Smuzhiyun #define RH_CLEAR_FEATURE        0x0100
90*4882a593Smuzhiyun #define RH_SET_FEATURE          0x0300
91*4882a593Smuzhiyun #define RH_SET_ADDRESS		0x0500
92*4882a593Smuzhiyun #define RH_GET_DESCRIPTOR	0x0680
93*4882a593Smuzhiyun #define RH_SET_DESCRIPTOR       0x0700
94*4882a593Smuzhiyun #define RH_GET_CONFIGURATION	0x0880
95*4882a593Smuzhiyun #define RH_SET_CONFIGURATION	0x0900
96*4882a593Smuzhiyun #define RH_GET_STATE            0x0280
97*4882a593Smuzhiyun #define RH_GET_INTERFACE        0x0A80
98*4882a593Smuzhiyun #define RH_SET_INTERFACE        0x0B00
99*4882a593Smuzhiyun #define RH_SYNC_FRAME           0x0C80
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep))
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #endif	/* __UBOOT_SL811_H */
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