1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * EHCI HCD (Host Controller Driver) for USB.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2013,2014 Renesas Electronics Corporation
5*4882a593Smuzhiyun * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/ehci-rmobile.h>
13*4882a593Smuzhiyun #include "ehci.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #if defined(CONFIG_R8A7740)
16*4882a593Smuzhiyun static u32 usb_base_address[] = {
17*4882a593Smuzhiyun 0xC6700000
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun #elif defined(CONFIG_R8A7790)
20*4882a593Smuzhiyun static u32 usb_base_address[] = {
21*4882a593Smuzhiyun 0xEE080000, /* USB0 (EHCI) */
22*4882a593Smuzhiyun 0xEE0A0000, /* USB1 */
23*4882a593Smuzhiyun 0xEE0C0000, /* USB2 */
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
26*4882a593Smuzhiyun defined(CONFIG_R8A7794)
27*4882a593Smuzhiyun static u32 usb_base_address[] = {
28*4882a593Smuzhiyun 0xEE080000, /* USB0 (EHCI) */
29*4882a593Smuzhiyun 0xEE0C0000, /* USB1 */
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun #else
32*4882a593Smuzhiyun #error rmobile EHCI USB driver not supported on this platform
33*4882a593Smuzhiyun #endif
34*4882a593Smuzhiyun
ehci_hcd_stop(int index)35*4882a593Smuzhiyun int ehci_hcd_stop(int index)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun int i;
38*4882a593Smuzhiyun u32 base;
39*4882a593Smuzhiyun struct ahbcom_pci_bridge *ahbcom_pci;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun base = usb_base_address[index];
42*4882a593Smuzhiyun ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
43*4882a593Smuzhiyun writel(0, &ahbcom_pci->ahb_bus_ctr);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* reset ehci */
46*4882a593Smuzhiyun setbits_le32(base + EHCI_USBCMD, CMD_RESET);
47*4882a593Smuzhiyun for (i = 100; i > 0; i--) {
48*4882a593Smuzhiyun if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
49*4882a593Smuzhiyun break;
50*4882a593Smuzhiyun udelay(100);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (!i)
54*4882a593Smuzhiyun printf("error : ehci(%d) reset failed.\n", index);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (index == (ARRAY_SIZE(usb_base_address) - 1))
57*4882a593Smuzhiyun setbits_le32(SMSTPCR7, SMSTPCR703);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)62*4882a593Smuzhiyun int ehci_hcd_init(int index, enum usb_init_type init,
63*4882a593Smuzhiyun struct ehci_hccr **hccr, struct ehci_hcor **hcor)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun u32 base;
66*4882a593Smuzhiyun u32 phys_base;
67*4882a593Smuzhiyun struct rmobile_ehci_reg *rehci;
68*4882a593Smuzhiyun struct ahbcom_pci_bridge *ahbcom_pci;
69*4882a593Smuzhiyun struct ahbconf_pci_bridge *ahbconf_pci;
70*4882a593Smuzhiyun struct ahb_pciconf *ahb_pciconf_ohci;
71*4882a593Smuzhiyun struct ahb_pciconf *ahb_pciconf_ehci;
72*4882a593Smuzhiyun uint32_t cap_base;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun base = usb_base_address[index];
75*4882a593Smuzhiyun phys_base = base;
76*4882a593Smuzhiyun if (index == 0)
77*4882a593Smuzhiyun clrbits_le32(SMSTPCR7, SMSTPCR703);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
80*4882a593Smuzhiyun ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
81*4882a593Smuzhiyun ahbconf_pci =
82*4882a593Smuzhiyun (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
83*4882a593Smuzhiyun ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
84*4882a593Smuzhiyun ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Clock & Reset & Direct Power Down */
87*4882a593Smuzhiyun clrsetbits_le32(&ahbcom_pci->usbctr,
88*4882a593Smuzhiyun (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
89*4882a593Smuzhiyun clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* AHB-PCI Bridge Communication Registers */
92*4882a593Smuzhiyun writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
93*4882a593Smuzhiyun writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
94*4882a593Smuzhiyun &ahbcom_pci->pciahb_win1_ctr);
95*4882a593Smuzhiyun writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
96*4882a593Smuzhiyun &ahbcom_pci->pciahb_win2_ctr);
97*4882a593Smuzhiyun writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
100*4882a593Smuzhiyun PCIBP_MODE | PCIREQ1 | PCIREQ0);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* PCI Configuration Registers for AHBPCI */
103*4882a593Smuzhiyun writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
104*4882a593Smuzhiyun &ahbcom_pci->ahbpci_win1_ctr);
105*4882a593Smuzhiyun writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
106*4882a593Smuzhiyun writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
107*4882a593Smuzhiyun writel(0xf0000000, &ahbconf_pci->win2_basead);
108*4882a593Smuzhiyun writel(SERREN | PERREN | MASTEREN | MEMEN,
109*4882a593Smuzhiyun &ahbconf_pci->cmnd_sts);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* PCI Configuration Registers for EHCI */
112*4882a593Smuzhiyun writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
113*4882a593Smuzhiyun writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
114*4882a593Smuzhiyun writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
115*4882a593Smuzhiyun writel(SERREN | PERREN | MASTEREN | MEMEN,
116*4882a593Smuzhiyun &ahb_pciconf_ohci->cmnd_sts);
117*4882a593Smuzhiyun writel(SERREN | PERREN | MASTEREN | MEMEN,
118*4882a593Smuzhiyun &ahb_pciconf_ehci->cmnd_sts);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Enable PCI interrupt */
121*4882a593Smuzhiyun setbits_le32(&ahbcom_pci->pci_int_enable,
122*4882a593Smuzhiyun USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
125*4882a593Smuzhiyun cap_base = ehci_readl(&(*hccr)->cr_capbase);
126*4882a593Smuzhiyun *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130