1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * drivers/usb/host/ehci-rcar_gen3.
3*4882a593Smuzhiyun * This file is EHCI HCD (Host Controller Driver) for USB.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015-2017 Renesas Electronics Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <wait_bit.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <usb/ehci-ci.h>
15*4882a593Smuzhiyun #include "ehci.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define EHCI_USBCMD 0x120
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define CORE_SPD_RSM_TIMSET 0x30c
22*4882a593Smuzhiyun #define CORE_OC_TIMSET 0x310
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Register offset */
25*4882a593Smuzhiyun #define AHB_OFFSET 0x200
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define BASE_HSUSB 0xE6590000
28*4882a593Smuzhiyun #define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
29*4882a593Smuzhiyun #define SUSPM 0x4000
30*4882a593Smuzhiyun #define SUSPM_NORMAL BIT(14)
31*4882a593Smuzhiyun #define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
32*4882a593Smuzhiyun #define USB0SEL 0x00000030
33*4882a593Smuzhiyun #define USB0SEL_EHCI 0x00000010
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define SMSTPCR7 0xE615014C
36*4882a593Smuzhiyun #define SMSTPCR700 BIT(0) /* EHCI3 */
37*4882a593Smuzhiyun #define SMSTPCR701 BIT(1) /* EHCI2 */
38*4882a593Smuzhiyun #define SMSTPCR702 BIT(2) /* EHCI1 */
39*4882a593Smuzhiyun #define SMSTPCR703 BIT(3) /* EHCI0 */
40*4882a593Smuzhiyun #define SMSTPCR704 BIT(4) /* HSUSB */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define AHB_PLL_RST BIT(1)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define USBH_INTBEN BIT(2)
45*4882a593Smuzhiyun #define USBH_INTAEN BIT(1)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define AHB_INT_ENABLE 0x200
48*4882a593Smuzhiyun #define AHB_USBCTR 0x20c
49*4882a593Smuzhiyun
ehci_hcd_stop(int index)50*4882a593Smuzhiyun int ehci_hcd_stop(int index)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun #if defined(CONFIG_R8A7795)
53*4882a593Smuzhiyun const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
54*4882a593Smuzhiyun #else
55*4882a593Smuzhiyun const u32 mask = SMSTPCR703 | SMSTPCR702;
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun const u32 base = RCAR_GEN3_USB_BASE(index);
58*4882a593Smuzhiyun int ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Reset EHCI */
61*4882a593Smuzhiyun setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
62*4882a593Smuzhiyun ret = wait_for_bit_le32((void *)(uintptr_t)base + EHCI_USBCMD,
63*4882a593Smuzhiyun CMD_RESET, false, 10, true);
64*4882a593Smuzhiyun if (ret) {
65*4882a593Smuzhiyun printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
66*4882a593Smuzhiyun index, ret);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun setbits_le32(SMSTPCR7, BIT(3 - index));
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if ((readl(SMSTPCR7) & mask) == mask)
72*4882a593Smuzhiyun setbits_le32(SMSTPCR7, SMSTPCR704);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)77*4882a593Smuzhiyun int ehci_hcd_init(int index, enum usb_init_type init,
78*4882a593Smuzhiyun struct ehci_hccr **hccr, struct ehci_hcor **hcor)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun const void __iomem *base =
81*4882a593Smuzhiyun (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
82*4882a593Smuzhiyun struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun clrbits_le32(SMSTPCR7, BIT(3 - index));
85*4882a593Smuzhiyun clrbits_le32(SMSTPCR7, SMSTPCR704);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
88*4882a593Smuzhiyun *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
89*4882a593Smuzhiyun HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Enable interrupt */
92*4882a593Smuzhiyun setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
93*4882a593Smuzhiyun writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
94*4882a593Smuzhiyun writel(0x000209ab, base + CORE_OC_TIMSET);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Choice USB0SEL */
97*4882a593Smuzhiyun clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Clock & Reset */
100*4882a593Smuzhiyun clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* low power status */
103*4882a593Smuzhiyun clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107