1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Freescale i.MX28 USB Host driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5*4882a593Smuzhiyun * on behalf of DENX Software Engineering GmbH
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
13*4882a593Smuzhiyun #include <errno.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "ehci.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* This DIGCTL register ungates clock to USB */
18*4882a593Smuzhiyun #define HW_DIGCTL_CTRL 0x8001c000
19*4882a593Smuzhiyun #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
20*4882a593Smuzhiyun #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct ehci_mxs_port {
23*4882a593Smuzhiyun uint32_t usb_regs;
24*4882a593Smuzhiyun struct mxs_usbphy_regs *phy_regs;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct mxs_register_32 *pll;
27*4882a593Smuzhiyun uint32_t pll_en_bits;
28*4882a593Smuzhiyun uint32_t pll_dis_bits;
29*4882a593Smuzhiyun uint32_t gate_bits;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct ehci_mxs_port mxs_port[] = {
33*4882a593Smuzhiyun #ifdef CONFIG_EHCI_MXS_PORT0
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun MXS_USBCTRL0_BASE,
36*4882a593Smuzhiyun (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
37*4882a593Smuzhiyun (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
38*4882a593Smuzhiyun offsetof(struct mxs_clkctrl_regs,
39*4882a593Smuzhiyun hw_clkctrl_pll0ctrl0_reg)),
40*4882a593Smuzhiyun CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
41*4882a593Smuzhiyun CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
42*4882a593Smuzhiyun HW_DIGCTL_CTRL_USB0_CLKGATE,
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun #ifdef CONFIG_EHCI_MXS_PORT1
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun MXS_USBCTRL1_BASE,
48*4882a593Smuzhiyun (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
49*4882a593Smuzhiyun (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
50*4882a593Smuzhiyun offsetof(struct mxs_clkctrl_regs,
51*4882a593Smuzhiyun hw_clkctrl_pll1ctrl0_reg)),
52*4882a593Smuzhiyun CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
53*4882a593Smuzhiyun CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
54*4882a593Smuzhiyun HW_DIGCTL_CTRL_USB1_CLKGATE,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
ehci_mxs_toggle_clock(const struct ehci_mxs_port * port,int enable)59*4882a593Smuzhiyun static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct mxs_register_32 *digctl_ctrl =
62*4882a593Smuzhiyun (struct mxs_register_32 *)HW_DIGCTL_CTRL;
63*4882a593Smuzhiyun int pll_offset, dig_offset;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (enable) {
66*4882a593Smuzhiyun pll_offset = offsetof(struct mxs_register_32, reg_set);
67*4882a593Smuzhiyun dig_offset = offsetof(struct mxs_register_32, reg_clr);
68*4882a593Smuzhiyun writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
69*4882a593Smuzhiyun writel(port->pll_en_bits, (u32)port->pll + pll_offset);
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun pll_offset = offsetof(struct mxs_register_32, reg_clr);
72*4882a593Smuzhiyun dig_offset = offsetof(struct mxs_register_32, reg_set);
73*4882a593Smuzhiyun writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
74*4882a593Smuzhiyun writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
board_ehci_hcd_init(int port)80*4882a593Smuzhiyun int __weak board_ehci_hcd_init(int port)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
board_ehci_hcd_exit(int port)85*4882a593Smuzhiyun int __weak board_ehci_hcd_exit(int port)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)90*4882a593Smuzhiyun int ehci_hcd_init(int index, enum usb_init_type init,
91*4882a593Smuzhiyun struct ehci_hccr **hccr, struct ehci_hcor **hcor)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun int ret;
95*4882a593Smuzhiyun uint32_t usb_base, cap_base;
96*4882a593Smuzhiyun const struct ehci_mxs_port *port;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
99*4882a593Smuzhiyun printf("Invalid port index (index = %d)!\n", index);
100*4882a593Smuzhiyun return -EINVAL;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun ret = board_ehci_hcd_init(index);
104*4882a593Smuzhiyun if (ret)
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun port = &mxs_port[index];
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Reset the PHY block */
110*4882a593Smuzhiyun writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
111*4882a593Smuzhiyun udelay(10);
112*4882a593Smuzhiyun writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
113*4882a593Smuzhiyun &port->phy_regs->hw_usbphy_ctrl_clr);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Enable USB clock */
116*4882a593Smuzhiyun ret = ehci_mxs_toggle_clock(port, 1);
117*4882a593Smuzhiyun if (ret)
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Start USB PHY */
121*4882a593Smuzhiyun writel(0, &port->phy_regs->hw_usbphy_pwd);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Enable UTMI+ Level 2 and Level 3 compatibility */
124*4882a593Smuzhiyun writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
125*4882a593Smuzhiyun &port->phy_regs->hw_usbphy_ctrl_set);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun usb_base = port->usb_regs + 0x100;
128*4882a593Smuzhiyun *hccr = (struct ehci_hccr *)usb_base;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun cap_base = ehci_readl(&(*hccr)->cr_capbase);
131*4882a593Smuzhiyun *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
ehci_hcd_stop(int index)136*4882a593Smuzhiyun int ehci_hcd_stop(int index)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun int ret;
139*4882a593Smuzhiyun uint32_t usb_base, cap_base, tmp;
140*4882a593Smuzhiyun struct ehci_hccr *hccr;
141*4882a593Smuzhiyun struct ehci_hcor *hcor;
142*4882a593Smuzhiyun const struct ehci_mxs_port *port;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
145*4882a593Smuzhiyun printf("Invalid port index (index = %d)!\n", index);
146*4882a593Smuzhiyun return -EINVAL;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun port = &mxs_port[index];
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* Stop the USB port */
152*4882a593Smuzhiyun usb_base = port->usb_regs + 0x100;
153*4882a593Smuzhiyun hccr = (struct ehci_hccr *)usb_base;
154*4882a593Smuzhiyun cap_base = ehci_readl(&hccr->cr_capbase);
155*4882a593Smuzhiyun hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun tmp = ehci_readl(&hcor->or_usbcmd);
158*4882a593Smuzhiyun tmp &= ~CMD_RUN;
159*4882a593Smuzhiyun ehci_writel(&hcor->or_usbcmd, tmp);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* Disable the PHY */
162*4882a593Smuzhiyun tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
163*4882a593Smuzhiyun USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
164*4882a593Smuzhiyun USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
165*4882a593Smuzhiyun USBPHY_PWD_TXPWDFS;
166*4882a593Smuzhiyun writel(tmp, &port->phy_regs->hw_usbphy_pwd);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Disable USB clock */
169*4882a593Smuzhiyun ret = ehci_mxs_toggle_clock(port, 0);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun board_ehci_hcd_exit(index);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return ret;
174*4882a593Smuzhiyun }
175