1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Faraday USB 2.0 EHCI Controller
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2010 Faraday Technology
5*4882a593Smuzhiyun * Dante Su <dantesu@faraday-tech.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <usb.h>
13*4882a593Smuzhiyun #include <usb/fusbh200.h>
14*4882a593Smuzhiyun #include <usb/fotg210.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "ehci.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifndef CONFIG_USB_EHCI_BASE_LIST
19*4882a593Smuzhiyun #define CONFIG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun union ehci_faraday_regs {
23*4882a593Smuzhiyun struct fusbh200_regs usb;
24*4882a593Smuzhiyun struct fotg210_regs otg;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
ehci_is_fotg2xx(union ehci_faraday_regs * regs)27*4882a593Smuzhiyun static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun return !readl(®s->usb.easstr);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
faraday_ehci_set_usbmode(struct ehci_ctrl * ctrl)32*4882a593Smuzhiyun void faraday_ehci_set_usbmode(struct ehci_ctrl *ctrl)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun /* nothing needs to be done */
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
faraday_ehci_get_port_speed(struct ehci_ctrl * ctrl,uint32_t reg)37*4882a593Smuzhiyun int faraday_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun int spd, ret = PORTSC_PSPD_HS;
40*4882a593Smuzhiyun union ehci_faraday_regs *regs;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ret = (void __iomem *)((ulong)ctrl->hcor - 0x10);
43*4882a593Smuzhiyun if (ehci_is_fotg2xx(regs))
44*4882a593Smuzhiyun spd = OTGCSR_SPD(readl(®s->otg.otgcsr));
45*4882a593Smuzhiyun else
46*4882a593Smuzhiyun spd = BMCSR_SPD(readl(®s->usb.bmcsr));
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun switch (spd) {
49*4882a593Smuzhiyun case 0: /* full speed */
50*4882a593Smuzhiyun ret = PORTSC_PSPD_FS;
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case 1: /* low speed */
53*4882a593Smuzhiyun ret = PORTSC_PSPD_LS;
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case 2: /* high speed */
56*4882a593Smuzhiyun ret = PORTSC_PSPD_HS;
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun default:
59*4882a593Smuzhiyun printf("ehci-faraday: invalid device speed\n");
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return ret;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
faraday_ehci_get_portsc_register(struct ehci_ctrl * ctrl,int port)66*4882a593Smuzhiyun uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun /* Faraday EHCI has one and only one portsc register */
69*4882a593Smuzhiyun if (port) {
70*4882a593Smuzhiyun /* Printing the message would cause a scan failure! */
71*4882a593Smuzhiyun debug("The request port(%d) is not configured\n", port);
72*4882a593Smuzhiyun return NULL;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Faraday EHCI PORTSC register offset is 0x20 from hcor */
76*4882a593Smuzhiyun return (uint32_t *)((uint8_t *)ctrl->hcor + 0x20);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct ehci_ops faraday_ehci_ops = {
80*4882a593Smuzhiyun .set_usb_mode = faraday_ehci_set_usbmode,
81*4882a593Smuzhiyun .get_port_speed = faraday_ehci_get_port_speed,
82*4882a593Smuzhiyun .get_portsc_register = faraday_ehci_get_portsc_register,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * Create the appropriate control structures to manage
87*4882a593Smuzhiyun * a new EHCI host controller.
88*4882a593Smuzhiyun */
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** ret_hccr,struct ehci_hcor ** ret_hcor)89*4882a593Smuzhiyun int ehci_hcd_init(int index, enum usb_init_type init,
90*4882a593Smuzhiyun struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct ehci_hccr *hccr;
93*4882a593Smuzhiyun struct ehci_hcor *hcor;
94*4882a593Smuzhiyun union ehci_faraday_regs *regs;
95*4882a593Smuzhiyun uint32_t base_list[] = CONFIG_USB_EHCI_BASE_LIST;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (index < 0 || index >= ARRAY_SIZE(base_list))
98*4882a593Smuzhiyun return -1;
99*4882a593Smuzhiyun ehci_set_controller_priv(index, NULL, &faraday_ehci_ops);
100*4882a593Smuzhiyun regs = (void __iomem *)base_list[index];
101*4882a593Smuzhiyun hccr = (struct ehci_hccr *)®s->usb.hccr;
102*4882a593Smuzhiyun hcor = (struct ehci_hcor *)®s->usb.hcor;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (ehci_is_fotg2xx(regs)) {
105*4882a593Smuzhiyun /* A-device bus reset */
106*4882a593Smuzhiyun /* ... Power off A-device */
107*4882a593Smuzhiyun setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
108*4882a593Smuzhiyun /* ... Drop vbus and bus traffic */
109*4882a593Smuzhiyun clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
110*4882a593Smuzhiyun mdelay(1);
111*4882a593Smuzhiyun /* ... Power on A-device */
112*4882a593Smuzhiyun clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
113*4882a593Smuzhiyun /* ... Drive vbus and bus traffic */
114*4882a593Smuzhiyun setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
115*4882a593Smuzhiyun mdelay(1);
116*4882a593Smuzhiyun /* Disable OTG & DEV interrupts, triggered at level-high */
117*4882a593Smuzhiyun writel(IMR_IRQLH | IMR_OTG | IMR_DEV, ®s->otg.imr);
118*4882a593Smuzhiyun /* Clear all interrupt status */
119*4882a593Smuzhiyun writel(ISR_HOST | ISR_OTG | ISR_DEV, ®s->otg.isr);
120*4882a593Smuzhiyun } else {
121*4882a593Smuzhiyun /* Interrupt=level-high */
122*4882a593Smuzhiyun setbits_le32(®s->usb.bmcsr, BMCSR_IRQLH);
123*4882a593Smuzhiyun /* VBUS on */
124*4882a593Smuzhiyun clrbits_le32(®s->usb.bmcsr, BMCSR_VBUS_OFF);
125*4882a593Smuzhiyun /* Disable all interrupts */
126*4882a593Smuzhiyun writel(0x00, ®s->usb.bmier);
127*4882a593Smuzhiyun writel(0x1f, ®s->usb.bmisr);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun *ret_hccr = hccr;
131*4882a593Smuzhiyun *ret_hcor = hcor;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun * Destroy the appropriate control structures corresponding
138*4882a593Smuzhiyun * the the EHCI host controller.
139*4882a593Smuzhiyun */
ehci_hcd_stop(int index)140*4882a593Smuzhiyun int ehci_hcd_stop(int index)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144