1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Faraday USB 2.0 OTG Controller
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2010 Faraday Technology
5*4882a593Smuzhiyun * Dante Su <dantesu@faraday-tech.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <command.h>
12*4882a593Smuzhiyun #include <config.h>
13*4882a593Smuzhiyun #include <net.h>
14*4882a593Smuzhiyun #include <malloc.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <linux/errno.h>
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/usb/ch9.h>
19*4882a593Smuzhiyun #include <linux/usb/gadget.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <usb/fotg210.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define CFG_NUM_ENDPOINTS 4
24*4882a593Smuzhiyun #define CFG_EP0_MAX_PACKET_SIZE 64
25*4882a593Smuzhiyun #define CFG_EPX_MAX_PACKET_SIZE 512
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct fotg210_chip;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct fotg210_ep {
32*4882a593Smuzhiyun struct usb_ep ep;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun uint maxpacket;
35*4882a593Smuzhiyun uint id;
36*4882a593Smuzhiyun uint stopped;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct list_head queue;
39*4882a593Smuzhiyun struct fotg210_chip *chip;
40*4882a593Smuzhiyun const struct usb_endpoint_descriptor *desc;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct fotg210_request {
44*4882a593Smuzhiyun struct usb_request req;
45*4882a593Smuzhiyun struct list_head queue;
46*4882a593Smuzhiyun struct fotg210_ep *ep;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct fotg210_chip {
50*4882a593Smuzhiyun struct usb_gadget gadget;
51*4882a593Smuzhiyun struct usb_gadget_driver *driver;
52*4882a593Smuzhiyun struct fotg210_regs *regs;
53*4882a593Smuzhiyun uint8_t irq;
54*4882a593Smuzhiyun uint16_t addr;
55*4882a593Smuzhiyun int pullup;
56*4882a593Smuzhiyun enum usb_device_state state;
57*4882a593Smuzhiyun struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS];
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct usb_endpoint_descriptor ep0_desc = {
61*4882a593Smuzhiyun .bLength = sizeof(struct usb_endpoint_descriptor),
62*4882a593Smuzhiyun .bDescriptorType = USB_DT_ENDPOINT,
63*4882a593Smuzhiyun .bEndpointAddress = USB_DIR_IN,
64*4882a593Smuzhiyun .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
fifo_to_ep(struct fotg210_chip * chip,int id,int in)67*4882a593Smuzhiyun static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return (id < 0) ? 0 : ((id & 0x03) + 1);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
ep_to_fifo(struct fotg210_chip * chip,int id)72*4882a593Smuzhiyun static inline int ep_to_fifo(struct fotg210_chip *chip, int id)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun return (id <= 0) ? -1 : ((id - 1) & 0x03);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
ep_reset(struct fotg210_chip * chip,uint8_t ep_addr)77*4882a593Smuzhiyun static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
80*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (ep_addr & USB_DIR_IN) {
83*4882a593Smuzhiyun /* reset endpoint */
84*4882a593Smuzhiyun setbits_le32(®s->iep[ep - 1], IEP_RESET);
85*4882a593Smuzhiyun mdelay(1);
86*4882a593Smuzhiyun clrbits_le32(®s->iep[ep - 1], IEP_RESET);
87*4882a593Smuzhiyun /* clear endpoint stall */
88*4882a593Smuzhiyun clrbits_le32(®s->iep[ep - 1], IEP_STALL);
89*4882a593Smuzhiyun } else {
90*4882a593Smuzhiyun /* reset endpoint */
91*4882a593Smuzhiyun setbits_le32(®s->oep[ep - 1], OEP_RESET);
92*4882a593Smuzhiyun mdelay(1);
93*4882a593Smuzhiyun clrbits_le32(®s->oep[ep - 1], OEP_RESET);
94*4882a593Smuzhiyun /* clear endpoint stall */
95*4882a593Smuzhiyun clrbits_le32(®s->oep[ep - 1], OEP_STALL);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
fotg210_reset(struct fotg210_chip * chip)101*4882a593Smuzhiyun static int fotg210_reset(struct fotg210_chip *chip)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
104*4882a593Smuzhiyun uint32_t i;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun chip->state = USB_STATE_POWERED;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* chip enable */
109*4882a593Smuzhiyun writel(DEVCTRL_EN, ®s->dev_ctrl);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* device address reset */
112*4882a593Smuzhiyun chip->addr = 0;
113*4882a593Smuzhiyun writel(0, ®s->dev_addr);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* set idle counter to 7ms */
116*4882a593Smuzhiyun writel(7, ®s->idle);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* disable all interrupts */
119*4882a593Smuzhiyun writel(IMR_MASK, ®s->imr);
120*4882a593Smuzhiyun writel(GIMR_MASK, ®s->gimr);
121*4882a593Smuzhiyun writel(GIMR0_MASK, ®s->gimr0);
122*4882a593Smuzhiyun writel(GIMR1_MASK, ®s->gimr1);
123*4882a593Smuzhiyun writel(GIMR2_MASK, ®s->gimr2);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* clear interrupts */
126*4882a593Smuzhiyun writel(ISR_MASK, ®s->isr);
127*4882a593Smuzhiyun writel(0, ®s->gisr);
128*4882a593Smuzhiyun writel(0, ®s->gisr0);
129*4882a593Smuzhiyun writel(0, ®s->gisr1);
130*4882a593Smuzhiyun writel(0, ®s->gisr2);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* chip reset */
133*4882a593Smuzhiyun setbits_le32(®s->dev_ctrl, DEVCTRL_RESET);
134*4882a593Smuzhiyun mdelay(10);
135*4882a593Smuzhiyun if (readl(®s->dev_ctrl) & DEVCTRL_RESET) {
136*4882a593Smuzhiyun printf("fotg210: chip reset failed\n");
137*4882a593Smuzhiyun return -1;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* CX FIFO reset */
141*4882a593Smuzhiyun setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR);
142*4882a593Smuzhiyun mdelay(10);
143*4882a593Smuzhiyun if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) {
144*4882a593Smuzhiyun printf("fotg210: ep0 fifo reset failed\n");
145*4882a593Smuzhiyun return -1;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */
149*4882a593Smuzhiyun writel(EPMAP14_DEFAULT, ®s->epmap14);
150*4882a593Smuzhiyun writel(EPMAP58_DEFAULT, ®s->epmap58);
151*4882a593Smuzhiyun writel(FIFOMAP_DEFAULT, ®s->fifomap);
152*4882a593Smuzhiyun writel(0, ®s->fifocfg);
153*4882a593Smuzhiyun for (i = 0; i < 8; ++i) {
154*4882a593Smuzhiyun writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]);
155*4882a593Smuzhiyun writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* FIFO reset */
159*4882a593Smuzhiyun for (i = 0; i < 4; ++i) {
160*4882a593Smuzhiyun writel(FIFOCSR_RESET, ®s->fifocsr[i]);
161*4882a593Smuzhiyun mdelay(10);
162*4882a593Smuzhiyun if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) {
163*4882a593Smuzhiyun printf("fotg210: fifo%d reset failed\n", i);
164*4882a593Smuzhiyun return -1;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* enable only device interrupt and triggered at level-high */
169*4882a593Smuzhiyun writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr);
170*4882a593Smuzhiyun writel(ISR_MASK, ®s->isr);
171*4882a593Smuzhiyun /* disable EP0 IN/OUT interrupt */
172*4882a593Smuzhiyun writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0);
173*4882a593Smuzhiyun /* disable EPX IN+SPK+OUT interrupts */
174*4882a593Smuzhiyun writel(GIMR1_MASK, ®s->gimr1);
175*4882a593Smuzhiyun /* disable wakeup+idle+dma+zlp interrupts */
176*4882a593Smuzhiyun writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN
177*4882a593Smuzhiyun | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2);
178*4882a593Smuzhiyun /* enable all group interrupt */
179*4882a593Smuzhiyun writel(0, ®s->gimr);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* suspend delay = 3 ms */
182*4882a593Smuzhiyun writel(3, ®s->idle);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* turn-on device interrupts */
185*4882a593Smuzhiyun setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
fotg210_cxwait(struct fotg210_chip * chip,uint32_t mask)190*4882a593Smuzhiyun static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
193*4882a593Smuzhiyun int ret = -1;
194*4882a593Smuzhiyun ulong ts;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
197*4882a593Smuzhiyun if ((readl(®s->cxfifo) & mask) != mask)
198*4882a593Smuzhiyun continue;
199*4882a593Smuzhiyun ret = 0;
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (ret)
204*4882a593Smuzhiyun printf("fotg210: cx/ep0 timeout\n");
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return ret;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
fotg210_dma(struct fotg210_ep * ep,struct fotg210_request * req)209*4882a593Smuzhiyun static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun struct fotg210_chip *chip = ep->chip;
212*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
213*4882a593Smuzhiyun uint32_t tmp, ts;
214*4882a593Smuzhiyun uint8_t *buf = req->req.buf + req->req.actual;
215*4882a593Smuzhiyun uint32_t len = req->req.length - req->req.actual;
216*4882a593Smuzhiyun int fifo = ep_to_fifo(chip, ep->id);
217*4882a593Smuzhiyun int ret = -EBUSY;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /* 1. init dma buffer */
220*4882a593Smuzhiyun if (len > ep->maxpacket)
221*4882a593Smuzhiyun len = ep->maxpacket;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* 2. wait for dma ready (hardware) */
224*4882a593Smuzhiyun for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
225*4882a593Smuzhiyun if (!(readl(®s->dma_ctrl) & DMACTRL_START)) {
226*4882a593Smuzhiyun ret = 0;
227*4882a593Smuzhiyun break;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun if (ret) {
231*4882a593Smuzhiyun printf("fotg210: dma busy\n");
232*4882a593Smuzhiyun req->req.status = ret;
233*4882a593Smuzhiyun return ret;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* 3. DMA target setup */
237*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN)
238*4882a593Smuzhiyun flush_dcache_range((ulong)buf, (ulong)buf + len);
239*4882a593Smuzhiyun else
240*4882a593Smuzhiyun invalidate_dcache_range((ulong)buf, (ulong)buf + len);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun writel(virt_to_phys(buf), ®s->dma_addr);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN) {
245*4882a593Smuzhiyun if (ep->id == 0) {
246*4882a593Smuzhiyun /* Wait until cx/ep0 fifo empty */
247*4882a593Smuzhiyun fotg210_cxwait(chip, CXFIFO_CXFIFOE);
248*4882a593Smuzhiyun udelay(1);
249*4882a593Smuzhiyun writel(DMAFIFO_CX, ®s->dma_fifo);
250*4882a593Smuzhiyun } else {
251*4882a593Smuzhiyun /* Wait until epx fifo empty */
252*4882a593Smuzhiyun fotg210_cxwait(chip, CXFIFO_FIFOE(fifo));
253*4882a593Smuzhiyun writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl);
256*4882a593Smuzhiyun } else {
257*4882a593Smuzhiyun uint32_t blen;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (ep->id == 0) {
260*4882a593Smuzhiyun writel(DMAFIFO_CX, ®s->dma_fifo);
261*4882a593Smuzhiyun do {
262*4882a593Smuzhiyun blen = CXFIFO_BYTES(readl(®s->cxfifo));
263*4882a593Smuzhiyun } while (blen < len);
264*4882a593Smuzhiyun } else {
265*4882a593Smuzhiyun writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
266*4882a593Smuzhiyun blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo]));
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun len = (len < blen) ? len : blen;
269*4882a593Smuzhiyun writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* 4. DMA start */
273*4882a593Smuzhiyun setbits_le32(®s->dma_ctrl, DMACTRL_START);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /* 5. DMA wait */
276*4882a593Smuzhiyun ret = -EBUSY;
277*4882a593Smuzhiyun for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
278*4882a593Smuzhiyun tmp = readl(®s->gisr2);
279*4882a593Smuzhiyun /* DMA complete */
280*4882a593Smuzhiyun if (tmp & GISR2_DMAFIN) {
281*4882a593Smuzhiyun ret = 0;
282*4882a593Smuzhiyun break;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun /* DMA error */
285*4882a593Smuzhiyun if (tmp & GISR2_DMAERR) {
286*4882a593Smuzhiyun printf("fotg210: dma error\n");
287*4882a593Smuzhiyun break;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun /* resume, suspend, reset */
290*4882a593Smuzhiyun if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) {
291*4882a593Smuzhiyun printf("fotg210: dma reset by host\n");
292*4882a593Smuzhiyun break;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* 7. DMA target reset */
297*4882a593Smuzhiyun if (ret)
298*4882a593Smuzhiyun writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun writel(0, ®s->gisr2);
301*4882a593Smuzhiyun writel(0, ®s->dma_fifo);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun req->req.status = ret;
304*4882a593Smuzhiyun if (!ret)
305*4882a593Smuzhiyun req->req.actual += len;
306*4882a593Smuzhiyun else
307*4882a593Smuzhiyun printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun return len;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /*
313*4882a593Smuzhiyun * result of setup packet
314*4882a593Smuzhiyun */
315*4882a593Smuzhiyun #define CX_IDLE 0
316*4882a593Smuzhiyun #define CX_FINISH 1
317*4882a593Smuzhiyun #define CX_STALL 2
318*4882a593Smuzhiyun
fotg210_setup(struct fotg210_chip * chip)319*4882a593Smuzhiyun static void fotg210_setup(struct fotg210_chip *chip)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun int id, ret = CX_IDLE;
322*4882a593Smuzhiyun uint32_t tmp[2];
323*4882a593Smuzhiyun struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp;
324*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /*
327*4882a593Smuzhiyun * If this is the first Cx 8 byte command,
328*4882a593Smuzhiyun * we can now query USB mode (high/full speed; USB 2.0/USB 1.0)
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun if (chip->state == USB_STATE_POWERED) {
331*4882a593Smuzhiyun chip->state = USB_STATE_DEFAULT;
332*4882a593Smuzhiyun if (readl(®s->otgcsr) & OTGCSR_DEV_B) {
333*4882a593Smuzhiyun /* Mini-B */
334*4882a593Smuzhiyun if (readl(®s->dev_ctrl) & DEVCTRL_HS) {
335*4882a593Smuzhiyun puts("fotg210: HS\n");
336*4882a593Smuzhiyun chip->gadget.speed = USB_SPEED_HIGH;
337*4882a593Smuzhiyun /* SOF mask timer = 1100 ticks */
338*4882a593Smuzhiyun writel(SOFMTR_TMR(1100), ®s->sof_mtr);
339*4882a593Smuzhiyun } else {
340*4882a593Smuzhiyun puts("fotg210: FS\n");
341*4882a593Smuzhiyun chip->gadget.speed = USB_SPEED_FULL;
342*4882a593Smuzhiyun /* SOF mask timer = 10000 ticks */
343*4882a593Smuzhiyun writel(SOFMTR_TMR(10000), ®s->sof_mtr);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun } else {
346*4882a593Smuzhiyun printf("fotg210: mini-A?\n");
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun /* switch data port to ep0 */
351*4882a593Smuzhiyun writel(DMAFIFO_CX, ®s->dma_fifo);
352*4882a593Smuzhiyun /* fetch 8 bytes setup packet */
353*4882a593Smuzhiyun tmp[0] = readl(®s->ep0_data);
354*4882a593Smuzhiyun tmp[1] = readl(®s->ep0_data);
355*4882a593Smuzhiyun /* release data port */
356*4882a593Smuzhiyun writel(0, ®s->dma_fifo);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (req->bRequestType & USB_DIR_IN)
359*4882a593Smuzhiyun ep0_desc.bEndpointAddress = USB_DIR_IN;
360*4882a593Smuzhiyun else
361*4882a593Smuzhiyun ep0_desc.bEndpointAddress = USB_DIR_OUT;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun ret = CX_IDLE;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
366*4882a593Smuzhiyun switch (req->bRequest) {
367*4882a593Smuzhiyun case USB_REQ_SET_CONFIGURATION:
368*4882a593Smuzhiyun debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF);
369*4882a593Smuzhiyun if (!(req->wValue & 0x00FF)) {
370*4882a593Smuzhiyun chip->state = USB_STATE_ADDRESS;
371*4882a593Smuzhiyun writel(chip->addr, ®s->dev_addr);
372*4882a593Smuzhiyun } else {
373*4882a593Smuzhiyun chip->state = USB_STATE_CONFIGURED;
374*4882a593Smuzhiyun writel(chip->addr | DEVADDR_CONF,
375*4882a593Smuzhiyun ®s->dev_addr);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun ret = CX_IDLE;
378*4882a593Smuzhiyun break;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun case USB_REQ_SET_ADDRESS:
381*4882a593Smuzhiyun debug("fotg210: set_addr(0x%04X)\n", req->wValue);
382*4882a593Smuzhiyun chip->state = USB_STATE_ADDRESS;
383*4882a593Smuzhiyun chip->addr = req->wValue & DEVADDR_ADDR_MASK;
384*4882a593Smuzhiyun ret = CX_FINISH;
385*4882a593Smuzhiyun writel(chip->addr, ®s->dev_addr);
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun case USB_REQ_CLEAR_FEATURE:
389*4882a593Smuzhiyun debug("fotg210: clr_feature(%d, %d)\n",
390*4882a593Smuzhiyun req->bRequestType & 0x03, req->wValue);
391*4882a593Smuzhiyun switch (req->wValue) {
392*4882a593Smuzhiyun case 0: /* [Endpoint] halt */
393*4882a593Smuzhiyun ep_reset(chip, req->wIndex);
394*4882a593Smuzhiyun ret = CX_FINISH;
395*4882a593Smuzhiyun break;
396*4882a593Smuzhiyun case 1: /* [Device] remote wake-up */
397*4882a593Smuzhiyun case 2: /* [Device] test mode */
398*4882a593Smuzhiyun default:
399*4882a593Smuzhiyun ret = CX_STALL;
400*4882a593Smuzhiyun break;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun case USB_REQ_SET_FEATURE:
405*4882a593Smuzhiyun debug("fotg210: set_feature(%d, %d)\n",
406*4882a593Smuzhiyun req->wValue, req->wIndex & 0xf);
407*4882a593Smuzhiyun switch (req->wValue) {
408*4882a593Smuzhiyun case 0: /* Endpoint Halt */
409*4882a593Smuzhiyun id = req->wIndex & 0xf;
410*4882a593Smuzhiyun setbits_le32(®s->iep[id - 1], IEP_STALL);
411*4882a593Smuzhiyun setbits_le32(®s->oep[id - 1], OEP_STALL);
412*4882a593Smuzhiyun ret = CX_FINISH;
413*4882a593Smuzhiyun break;
414*4882a593Smuzhiyun case 1: /* Remote Wakeup */
415*4882a593Smuzhiyun case 2: /* Test Mode */
416*4882a593Smuzhiyun default:
417*4882a593Smuzhiyun ret = CX_STALL;
418*4882a593Smuzhiyun break;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun break;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun case USB_REQ_GET_STATUS:
423*4882a593Smuzhiyun debug("fotg210: get_status\n");
424*4882a593Smuzhiyun ret = CX_STALL;
425*4882a593Smuzhiyun break;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun case USB_REQ_SET_DESCRIPTOR:
428*4882a593Smuzhiyun debug("fotg210: set_descriptor\n");
429*4882a593Smuzhiyun ret = CX_STALL;
430*4882a593Smuzhiyun break;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun case USB_REQ_SYNCH_FRAME:
433*4882a593Smuzhiyun debug("fotg210: sync frame\n");
434*4882a593Smuzhiyun ret = CX_STALL;
435*4882a593Smuzhiyun break;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun if (ret == CX_IDLE && chip->driver->setup) {
440*4882a593Smuzhiyun if (chip->driver->setup(&chip->gadget, req) < 0)
441*4882a593Smuzhiyun ret = CX_STALL;
442*4882a593Smuzhiyun else
443*4882a593Smuzhiyun ret = CX_FINISH;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun switch (ret) {
447*4882a593Smuzhiyun case CX_FINISH:
448*4882a593Smuzhiyun setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun case CX_STALL:
452*4882a593Smuzhiyun setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN);
453*4882a593Smuzhiyun printf("fotg210: cx_stall!\n");
454*4882a593Smuzhiyun break;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun case CX_IDLE:
457*4882a593Smuzhiyun debug("fotg210: cx_idle?\n");
458*4882a593Smuzhiyun default:
459*4882a593Smuzhiyun break;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun /*
464*4882a593Smuzhiyun * fifo - FIFO id
465*4882a593Smuzhiyun * zlp - zero length packet
466*4882a593Smuzhiyun */
fotg210_recv(struct fotg210_chip * chip,int ep_id)467*4882a593Smuzhiyun static void fotg210_recv(struct fotg210_chip *chip, int ep_id)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
470*4882a593Smuzhiyun struct fotg210_ep *ep = chip->ep + ep_id;
471*4882a593Smuzhiyun struct fotg210_request *req;
472*4882a593Smuzhiyun int len;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
475*4882a593Smuzhiyun printf("fotg210: ep%d recv, invalid!\n", ep->id);
476*4882a593Smuzhiyun return;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun if (list_empty(&ep->queue)) {
480*4882a593Smuzhiyun printf("fotg210: ep%d recv, drop!\n", ep->id);
481*4882a593Smuzhiyun return;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun req = list_first_entry(&ep->queue, struct fotg210_request, queue);
485*4882a593Smuzhiyun len = fotg210_dma(ep, req);
486*4882a593Smuzhiyun if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) {
487*4882a593Smuzhiyun list_del_init(&req->queue);
488*4882a593Smuzhiyun if (req->req.complete)
489*4882a593Smuzhiyun req->req.complete(&ep->ep, &req->req);
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun if (ep->id > 0 && list_empty(&ep->queue)) {
493*4882a593Smuzhiyun setbits_le32(®s->gimr1,
494*4882a593Smuzhiyun GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun /*
499*4882a593Smuzhiyun * USB Gadget Layer
500*4882a593Smuzhiyun */
fotg210_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)501*4882a593Smuzhiyun static int fotg210_ep_enable(
502*4882a593Smuzhiyun struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
505*4882a593Smuzhiyun struct fotg210_chip *chip = ep->chip;
506*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
507*4882a593Smuzhiyun int id = ep_to_fifo(chip, ep->id);
508*4882a593Smuzhiyun int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun if (!_ep || !desc
511*4882a593Smuzhiyun || desc->bDescriptorType != USB_DT_ENDPOINT
512*4882a593Smuzhiyun || le16_to_cpu(desc->wMaxPacketSize) == 0) {
513*4882a593Smuzhiyun printf("fotg210: bad ep or descriptor\n");
514*4882a593Smuzhiyun return -EINVAL;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun ep->desc = desc;
518*4882a593Smuzhiyun ep->stopped = 0;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (in)
521*4882a593Smuzhiyun setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN));
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
524*4882a593Smuzhiyun case USB_ENDPOINT_XFER_CONTROL:
525*4882a593Smuzhiyun return -EINVAL;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun case USB_ENDPOINT_XFER_ISOC:
528*4882a593Smuzhiyun setbits_le32(®s->fifocfg,
529*4882a593Smuzhiyun FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC));
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun case USB_ENDPOINT_XFER_BULK:
533*4882a593Smuzhiyun setbits_le32(®s->fifocfg,
534*4882a593Smuzhiyun FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK));
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun case USB_ENDPOINT_XFER_INT:
538*4882a593Smuzhiyun setbits_le32(®s->fifocfg,
539*4882a593Smuzhiyun FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR));
540*4882a593Smuzhiyun break;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun return 0;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
fotg210_ep_disable(struct usb_ep * _ep)546*4882a593Smuzhiyun static int fotg210_ep_disable(struct usb_ep *_ep)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
549*4882a593Smuzhiyun struct fotg210_chip *chip = ep->chip;
550*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
551*4882a593Smuzhiyun int id = ep_to_fifo(chip, ep->id);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun ep->desc = NULL;
554*4882a593Smuzhiyun ep->stopped = 1;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK));
557*4882a593Smuzhiyun clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK));
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun return 0;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
fotg210_ep_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)562*4882a593Smuzhiyun static struct usb_request *fotg210_ep_alloc_request(
563*4882a593Smuzhiyun struct usb_ep *_ep, gfp_t gfp_flags)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun struct fotg210_request *req = malloc(sizeof(*req));
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun if (req) {
568*4882a593Smuzhiyun memset(req, 0, sizeof(*req));
569*4882a593Smuzhiyun INIT_LIST_HEAD(&req->queue);
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun return &req->req;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
fotg210_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)574*4882a593Smuzhiyun static void fotg210_ep_free_request(
575*4882a593Smuzhiyun struct usb_ep *_ep, struct usb_request *_req)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun struct fotg210_request *req;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun req = container_of(_req, struct fotg210_request, req);
580*4882a593Smuzhiyun free(req);
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
fotg210_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)583*4882a593Smuzhiyun static int fotg210_ep_queue(
584*4882a593Smuzhiyun struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
587*4882a593Smuzhiyun struct fotg210_chip *chip = ep->chip;
588*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
589*4882a593Smuzhiyun struct fotg210_request *req;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun req = container_of(_req, struct fotg210_request, req);
592*4882a593Smuzhiyun if (!_req || !_req->complete || !_req->buf
593*4882a593Smuzhiyun || !list_empty(&req->queue)) {
594*4882a593Smuzhiyun printf("fotg210: invalid request to ep%d\n", ep->id);
595*4882a593Smuzhiyun return -EINVAL;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (!chip || chip->state == USB_STATE_SUSPENDED) {
599*4882a593Smuzhiyun printf("fotg210: request while chip suspended\n");
600*4882a593Smuzhiyun return -EINVAL;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun req->req.actual = 0;
604*4882a593Smuzhiyun req->req.status = -EINPROGRESS;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun if (req->req.length == 0) {
607*4882a593Smuzhiyun req->req.status = 0;
608*4882a593Smuzhiyun if (req->req.complete)
609*4882a593Smuzhiyun req->req.complete(&ep->ep, &req->req);
610*4882a593Smuzhiyun return 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (ep->id == 0) {
614*4882a593Smuzhiyun do {
615*4882a593Smuzhiyun int len = fotg210_dma(ep, req);
616*4882a593Smuzhiyun if (len < ep->ep.maxpacket)
617*4882a593Smuzhiyun break;
618*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN)
619*4882a593Smuzhiyun udelay(100);
620*4882a593Smuzhiyun } while (req->req.length > req->req.actual);
621*4882a593Smuzhiyun } else {
622*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN) {
623*4882a593Smuzhiyun do {
624*4882a593Smuzhiyun int len = fotg210_dma(ep, req);
625*4882a593Smuzhiyun if (len < ep->ep.maxpacket)
626*4882a593Smuzhiyun break;
627*4882a593Smuzhiyun } while (req->req.length > req->req.actual);
628*4882a593Smuzhiyun } else {
629*4882a593Smuzhiyun list_add_tail(&req->queue, &ep->queue);
630*4882a593Smuzhiyun clrbits_le32(®s->gimr1,
631*4882a593Smuzhiyun GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
636*4882a593Smuzhiyun if (req->req.complete)
637*4882a593Smuzhiyun req->req.complete(&ep->ep, &req->req);
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun return 0;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
fotg210_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)643*4882a593Smuzhiyun static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
646*4882a593Smuzhiyun struct fotg210_request *req;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /* make sure it's actually queued on this endpoint */
649*4882a593Smuzhiyun list_for_each_entry(req, &ep->queue, queue) {
650*4882a593Smuzhiyun if (&req->req == _req)
651*4882a593Smuzhiyun break;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun if (&req->req != _req)
654*4882a593Smuzhiyun return -EINVAL;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun /* remove the request */
657*4882a593Smuzhiyun list_del_init(&req->queue);
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun /* update status & invoke complete callback */
660*4882a593Smuzhiyun if (req->req.status == -EINPROGRESS) {
661*4882a593Smuzhiyun req->req.status = -ECONNRESET;
662*4882a593Smuzhiyun if (req->req.complete)
663*4882a593Smuzhiyun req->req.complete(_ep, &req->req);
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun return 0;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
fotg210_ep_halt(struct usb_ep * _ep,int halt)669*4882a593Smuzhiyun static int fotg210_ep_halt(struct usb_ep *_ep, int halt)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
672*4882a593Smuzhiyun struct fotg210_chip *chip = ep->chip;
673*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
674*4882a593Smuzhiyun int ret = -1;
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun debug("fotg210: ep%d halt=%d\n", ep->id, halt);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun /* Endpoint STALL */
679*4882a593Smuzhiyun if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) {
680*4882a593Smuzhiyun if (halt) {
681*4882a593Smuzhiyun /* wait until all ep fifo empty */
682*4882a593Smuzhiyun fotg210_cxwait(chip, 0xf00);
683*4882a593Smuzhiyun /* stall */
684*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN) {
685*4882a593Smuzhiyun setbits_le32(®s->iep[ep->id - 1],
686*4882a593Smuzhiyun IEP_STALL);
687*4882a593Smuzhiyun } else {
688*4882a593Smuzhiyun setbits_le32(®s->oep[ep->id - 1],
689*4882a593Smuzhiyun OEP_STALL);
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun } else {
692*4882a593Smuzhiyun if (ep->desc->bEndpointAddress & USB_DIR_IN) {
693*4882a593Smuzhiyun clrbits_le32(®s->iep[ep->id - 1],
694*4882a593Smuzhiyun IEP_STALL);
695*4882a593Smuzhiyun } else {
696*4882a593Smuzhiyun clrbits_le32(®s->oep[ep->id - 1],
697*4882a593Smuzhiyun OEP_STALL);
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun ret = 0;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return ret;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun /*
707*4882a593Smuzhiyun * activate/deactivate link with host.
708*4882a593Smuzhiyun */
pullup(struct fotg210_chip * chip,int is_on)709*4882a593Smuzhiyun static void pullup(struct fotg210_chip *chip, int is_on)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun if (is_on) {
714*4882a593Smuzhiyun if (!chip->pullup) {
715*4882a593Smuzhiyun chip->state = USB_STATE_POWERED;
716*4882a593Smuzhiyun chip->pullup = 1;
717*4882a593Smuzhiyun /* enable the chip */
718*4882a593Smuzhiyun setbits_le32(®s->dev_ctrl, DEVCTRL_EN);
719*4882a593Smuzhiyun /* clear unplug bit (BIT0) */
720*4882a593Smuzhiyun clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun } else {
723*4882a593Smuzhiyun chip->state = USB_STATE_NOTATTACHED;
724*4882a593Smuzhiyun chip->pullup = 0;
725*4882a593Smuzhiyun chip->addr = 0;
726*4882a593Smuzhiyun writel(chip->addr, ®s->dev_addr);
727*4882a593Smuzhiyun /* set unplug bit (BIT0) */
728*4882a593Smuzhiyun setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
729*4882a593Smuzhiyun /* disable the chip */
730*4882a593Smuzhiyun clrbits_le32(®s->dev_ctrl, DEVCTRL_EN);
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
fotg210_pullup(struct usb_gadget * _gadget,int is_on)734*4882a593Smuzhiyun static int fotg210_pullup(struct usb_gadget *_gadget, int is_on)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun struct fotg210_chip *chip;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun chip = container_of(_gadget, struct fotg210_chip, gadget);
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun debug("fotg210: pullup=%d\n", is_on);
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun pullup(chip, is_on);
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun return 0;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
fotg210_get_frame(struct usb_gadget * _gadget)747*4882a593Smuzhiyun static int fotg210_get_frame(struct usb_gadget *_gadget)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun struct fotg210_chip *chip;
750*4882a593Smuzhiyun struct fotg210_regs *regs;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun chip = container_of(_gadget, struct fotg210_chip, gadget);
753*4882a593Smuzhiyun regs = chip->regs;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun return SOFFNR_FNR(readl(®s->sof_fnr));
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun static struct usb_gadget_ops fotg210_gadget_ops = {
759*4882a593Smuzhiyun .get_frame = fotg210_get_frame,
760*4882a593Smuzhiyun .pullup = fotg210_pullup,
761*4882a593Smuzhiyun };
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun static struct usb_ep_ops fotg210_ep_ops = {
764*4882a593Smuzhiyun .enable = fotg210_ep_enable,
765*4882a593Smuzhiyun .disable = fotg210_ep_disable,
766*4882a593Smuzhiyun .queue = fotg210_ep_queue,
767*4882a593Smuzhiyun .dequeue = fotg210_ep_dequeue,
768*4882a593Smuzhiyun .set_halt = fotg210_ep_halt,
769*4882a593Smuzhiyun .alloc_request = fotg210_ep_alloc_request,
770*4882a593Smuzhiyun .free_request = fotg210_ep_free_request,
771*4882a593Smuzhiyun };
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun static struct fotg210_chip controller = {
774*4882a593Smuzhiyun .regs = (void __iomem *)CONFIG_FOTG210_BASE,
775*4882a593Smuzhiyun .gadget = {
776*4882a593Smuzhiyun .name = "fotg210_udc",
777*4882a593Smuzhiyun .ops = &fotg210_gadget_ops,
778*4882a593Smuzhiyun .ep0 = &controller.ep[0].ep,
779*4882a593Smuzhiyun .speed = USB_SPEED_UNKNOWN,
780*4882a593Smuzhiyun .is_dualspeed = 1,
781*4882a593Smuzhiyun .is_otg = 0,
782*4882a593Smuzhiyun .is_a_peripheral = 0,
783*4882a593Smuzhiyun .b_hnp_enable = 0,
784*4882a593Smuzhiyun .a_hnp_support = 0,
785*4882a593Smuzhiyun .a_alt_hnp_support = 0,
786*4882a593Smuzhiyun },
787*4882a593Smuzhiyun .ep[0] = {
788*4882a593Smuzhiyun .id = 0,
789*4882a593Smuzhiyun .ep = {
790*4882a593Smuzhiyun .name = "ep0",
791*4882a593Smuzhiyun .ops = &fotg210_ep_ops,
792*4882a593Smuzhiyun },
793*4882a593Smuzhiyun .desc = &ep0_desc,
794*4882a593Smuzhiyun .chip = &controller,
795*4882a593Smuzhiyun .maxpacket = CFG_EP0_MAX_PACKET_SIZE,
796*4882a593Smuzhiyun },
797*4882a593Smuzhiyun .ep[1] = {
798*4882a593Smuzhiyun .id = 1,
799*4882a593Smuzhiyun .ep = {
800*4882a593Smuzhiyun .name = "ep1",
801*4882a593Smuzhiyun .ops = &fotg210_ep_ops,
802*4882a593Smuzhiyun },
803*4882a593Smuzhiyun .chip = &controller,
804*4882a593Smuzhiyun .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
805*4882a593Smuzhiyun },
806*4882a593Smuzhiyun .ep[2] = {
807*4882a593Smuzhiyun .id = 2,
808*4882a593Smuzhiyun .ep = {
809*4882a593Smuzhiyun .name = "ep2",
810*4882a593Smuzhiyun .ops = &fotg210_ep_ops,
811*4882a593Smuzhiyun },
812*4882a593Smuzhiyun .chip = &controller,
813*4882a593Smuzhiyun .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
814*4882a593Smuzhiyun },
815*4882a593Smuzhiyun .ep[3] = {
816*4882a593Smuzhiyun .id = 3,
817*4882a593Smuzhiyun .ep = {
818*4882a593Smuzhiyun .name = "ep3",
819*4882a593Smuzhiyun .ops = &fotg210_ep_ops,
820*4882a593Smuzhiyun },
821*4882a593Smuzhiyun .chip = &controller,
822*4882a593Smuzhiyun .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
823*4882a593Smuzhiyun },
824*4882a593Smuzhiyun .ep[4] = {
825*4882a593Smuzhiyun .id = 4,
826*4882a593Smuzhiyun .ep = {
827*4882a593Smuzhiyun .name = "ep4",
828*4882a593Smuzhiyun .ops = &fotg210_ep_ops,
829*4882a593Smuzhiyun },
830*4882a593Smuzhiyun .chip = &controller,
831*4882a593Smuzhiyun .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
832*4882a593Smuzhiyun },
833*4882a593Smuzhiyun };
834*4882a593Smuzhiyun
usb_gadget_handle_interrupts(int index)835*4882a593Smuzhiyun int usb_gadget_handle_interrupts(int index)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun struct fotg210_chip *chip = &controller;
838*4882a593Smuzhiyun struct fotg210_regs *regs = chip->regs;
839*4882a593Smuzhiyun uint32_t id, st, isr, gisr;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun isr = readl(®s->isr) & (~readl(®s->imr));
842*4882a593Smuzhiyun gisr = readl(®s->gisr) & (~readl(®s->gimr));
843*4882a593Smuzhiyun if (!(isr & ISR_DEV) || !gisr)
844*4882a593Smuzhiyun return 0;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun writel(ISR_DEV, ®s->isr);
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun /* CX interrupts */
849*4882a593Smuzhiyun if (gisr & GISR_GRP0) {
850*4882a593Smuzhiyun st = readl(®s->gisr0);
851*4882a593Smuzhiyun /*
852*4882a593Smuzhiyun * Write 1 and then 0 works for both W1C & RW.
853*4882a593Smuzhiyun *
854*4882a593Smuzhiyun * HW v1.11.0+: It's a W1C register (write 1 clear)
855*4882a593Smuzhiyun * HW v1.10.0-: It's a R/W register (write 0 clear)
856*4882a593Smuzhiyun */
857*4882a593Smuzhiyun writel(st & GISR0_CXABORT, ®s->gisr0);
858*4882a593Smuzhiyun writel(0, ®s->gisr0);
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun if (st & GISR0_CXERR)
861*4882a593Smuzhiyun printf("fotg210: cmd error\n");
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun if (st & GISR0_CXABORT)
864*4882a593Smuzhiyun printf("fotg210: cmd abort\n");
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun if (st & GISR0_CXSETUP) /* setup */
867*4882a593Smuzhiyun fotg210_setup(chip);
868*4882a593Smuzhiyun else if (st & GISR0_CXEND) /* command finish */
869*4882a593Smuzhiyun setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun /* FIFO interrupts */
873*4882a593Smuzhiyun if (gisr & GISR_GRP1) {
874*4882a593Smuzhiyun st = readl(®s->gisr1);
875*4882a593Smuzhiyun for (id = 0; id < 4; ++id) {
876*4882a593Smuzhiyun if (st & GISR1_RX_FIFO(id))
877*4882a593Smuzhiyun fotg210_recv(chip, fifo_to_ep(chip, id, 0));
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun /* Device Status Interrupts */
882*4882a593Smuzhiyun if (gisr & GISR_GRP2) {
883*4882a593Smuzhiyun st = readl(®s->gisr2);
884*4882a593Smuzhiyun /*
885*4882a593Smuzhiyun * Write 1 and then 0 works for both W1C & RW.
886*4882a593Smuzhiyun *
887*4882a593Smuzhiyun * HW v1.11.0+: It's a W1C register (write 1 clear)
888*4882a593Smuzhiyun * HW v1.10.0-: It's a R/W register (write 0 clear)
889*4882a593Smuzhiyun */
890*4882a593Smuzhiyun writel(st, ®s->gisr2);
891*4882a593Smuzhiyun writel(0, ®s->gisr2);
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun if (st & GISR2_RESET)
894*4882a593Smuzhiyun printf("fotg210: reset by host\n");
895*4882a593Smuzhiyun else if (st & GISR2_SUSPEND)
896*4882a593Smuzhiyun printf("fotg210: suspend/removed\n");
897*4882a593Smuzhiyun else if (st & GISR2_RESUME)
898*4882a593Smuzhiyun printf("fotg210: resume\n");
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun /* Errors */
901*4882a593Smuzhiyun if (st & GISR2_ISOCERR)
902*4882a593Smuzhiyun printf("fotg210: iso error\n");
903*4882a593Smuzhiyun if (st & GISR2_ISOCABT)
904*4882a593Smuzhiyun printf("fotg210: iso abort\n");
905*4882a593Smuzhiyun if (st & GISR2_DMAERR)
906*4882a593Smuzhiyun printf("fotg210: dma error\n");
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun return 0;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
usb_gadget_register_driver(struct usb_gadget_driver * driver)912*4882a593Smuzhiyun int usb_gadget_register_driver(struct usb_gadget_driver *driver)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun int i, ret = 0;
915*4882a593Smuzhiyun struct fotg210_chip *chip = &controller;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun if (!driver || !driver->bind || !driver->setup) {
918*4882a593Smuzhiyun puts("fotg210: bad parameter.\n");
919*4882a593Smuzhiyun return -EINVAL;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun INIT_LIST_HEAD(&chip->gadget.ep_list);
923*4882a593Smuzhiyun for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) {
924*4882a593Smuzhiyun struct fotg210_ep *ep = chip->ep + i;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun ep->ep.maxpacket = ep->maxpacket;
927*4882a593Smuzhiyun INIT_LIST_HEAD(&ep->queue);
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun if (ep->id == 0) {
930*4882a593Smuzhiyun ep->stopped = 0;
931*4882a593Smuzhiyun } else {
932*4882a593Smuzhiyun ep->stopped = 1;
933*4882a593Smuzhiyun list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list);
934*4882a593Smuzhiyun }
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun if (fotg210_reset(chip)) {
938*4882a593Smuzhiyun puts("fotg210: reset failed.\n");
939*4882a593Smuzhiyun return -EINVAL;
940*4882a593Smuzhiyun }
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun ret = driver->bind(&chip->gadget);
943*4882a593Smuzhiyun if (ret) {
944*4882a593Smuzhiyun debug("fotg210: driver->bind() returned %d\n", ret);
945*4882a593Smuzhiyun return ret;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun chip->driver = driver;
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun return ret;
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
usb_gadget_unregister_driver(struct usb_gadget_driver * driver)952*4882a593Smuzhiyun int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
953*4882a593Smuzhiyun {
954*4882a593Smuzhiyun struct fotg210_chip *chip = &controller;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun driver->unbind(&chip->gadget);
957*4882a593Smuzhiyun chip->driver = NULL;
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun pullup(chip, 0);
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun return 0;
962*4882a593Smuzhiyun }
963