1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011, Marvell Semiconductor Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the GPL-2 or later. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __GADGET__CI_UDC_H__ 7*4882a593Smuzhiyun #define __GADGET__CI_UDC_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define NUM_ENDPOINTS 6 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifdef CONFIG_CI_UDC_HAS_HOSTPC 12*4882a593Smuzhiyun struct ci_udc { 13*4882a593Smuzhiyun u32 usbcmd; /* 0x130 */ 14*4882a593Smuzhiyun u32 usbsts; /* 0x134 */ 15*4882a593Smuzhiyun u32 pad1[3]; 16*4882a593Smuzhiyun u32 devaddr; /* 0x144 */ 17*4882a593Smuzhiyun u32 epinitaddr; /* 0x148 */ 18*4882a593Smuzhiyun u32 pad2[10]; 19*4882a593Smuzhiyun u32 portsc; /* 0x174 */ 20*4882a593Smuzhiyun u32 pad178[(0x1b4 - (0x174 + 4)) / 4]; 21*4882a593Smuzhiyun u32 hostpc1_devlc; /* 0x1b4 */ 22*4882a593Smuzhiyun u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4]; 23*4882a593Smuzhiyun u32 usbmode; /* 0x1f8 */ 24*4882a593Smuzhiyun u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4]; 25*4882a593Smuzhiyun u32 epsetupstat; /* 0x208 */ 26*4882a593Smuzhiyun u32 epprime; /* 0x20c */ 27*4882a593Smuzhiyun u32 epflush; /* 0x210 */ 28*4882a593Smuzhiyun u32 epstat; /* 0x214 */ 29*4882a593Smuzhiyun u32 epcomp; /* 0x218 */ 30*4882a593Smuzhiyun u32 epctrl[16]; /* 0x21c */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun #else 33*4882a593Smuzhiyun struct ci_udc { 34*4882a593Smuzhiyun u32 usbcmd; /* 0x140 */ 35*4882a593Smuzhiyun u32 usbsts; /* 0x144 */ 36*4882a593Smuzhiyun u32 pad1[3]; 37*4882a593Smuzhiyun u32 devaddr; /* 0x154 */ 38*4882a593Smuzhiyun u32 epinitaddr; /* 0x158 */ 39*4882a593Smuzhiyun u32 pad2[10]; 40*4882a593Smuzhiyun u32 portsc; /* 0x184 */ 41*4882a593Smuzhiyun u32 pad3[8]; 42*4882a593Smuzhiyun u32 usbmode; /* 0x1a8 */ 43*4882a593Smuzhiyun u32 epstat; /* 0x1ac */ 44*4882a593Smuzhiyun u32 epprime; /* 0x1b0 */ 45*4882a593Smuzhiyun u32 epflush; /* 0x1b4 */ 46*4882a593Smuzhiyun u32 pad4; 47*4882a593Smuzhiyun u32 epcomp; /* 0x1bc */ 48*4882a593Smuzhiyun u32 epctrl[16]; /* 0x1c0 */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PTS_ENABLE 2 52*4882a593Smuzhiyun #define PTS(x) (((x) & 0x3) << 30) 53*4882a593Smuzhiyun #define PFSC (1 << 24) 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MICRO_8FRAME 0x8 57*4882a593Smuzhiyun #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) 58*4882a593Smuzhiyun #define USBCMD_FS2 (1 << 15) 59*4882a593Smuzhiyun #define USBCMD_RST (1 << 1) 60*4882a593Smuzhiyun #define USBCMD_RUN (1) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define STS_SLI (1 << 8) 63*4882a593Smuzhiyun #define STS_URI (1 << 6) 64*4882a593Smuzhiyun #define STS_PCI (1 << 2) 65*4882a593Smuzhiyun #define STS_UEI (1 << 1) 66*4882a593Smuzhiyun #define STS_UI (1 << 0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define USBMODE_DEVICE 2 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) 71*4882a593Smuzhiyun #define EPT_RX(x) (1 << ((x) & 0xffff)) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CTRL_TXE (1 << 23) 74*4882a593Smuzhiyun #define CTRL_TXR (1 << 22) 75*4882a593Smuzhiyun #define CTRL_RXE (1 << 7) 76*4882a593Smuzhiyun #define CTRL_RXR (1 << 6) 77*4882a593Smuzhiyun #define CTRL_TXT_BULK (2 << 18) 78*4882a593Smuzhiyun #define CTRL_RXT_BULK (2 << 2) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct ci_req { 81*4882a593Smuzhiyun struct usb_request req; 82*4882a593Smuzhiyun struct list_head queue; 83*4882a593Smuzhiyun /* Bounce buffer allocated if needed to align the transfer */ 84*4882a593Smuzhiyun uint8_t *b_buf; 85*4882a593Smuzhiyun uint32_t b_len; 86*4882a593Smuzhiyun /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ 87*4882a593Smuzhiyun uint8_t *hw_buf; 88*4882a593Smuzhiyun uint32_t hw_len; 89*4882a593Smuzhiyun uint32_t dtd_count; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun struct ci_ep { 93*4882a593Smuzhiyun struct usb_ep ep; 94*4882a593Smuzhiyun struct list_head queue; 95*4882a593Smuzhiyun bool req_primed; 96*4882a593Smuzhiyun const struct usb_endpoint_descriptor *desc; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct ci_drv { 100*4882a593Smuzhiyun struct usb_gadget gadget; 101*4882a593Smuzhiyun struct ci_req *ep0_req; 102*4882a593Smuzhiyun bool ep0_data_phase; 103*4882a593Smuzhiyun struct usb_gadget_driver *driver; 104*4882a593Smuzhiyun struct ehci_ctrl *ctrl; 105*4882a593Smuzhiyun struct ept_queue_head *epts; 106*4882a593Smuzhiyun uint8_t *items_mem; 107*4882a593Smuzhiyun struct ci_ep ep[NUM_ENDPOINTS]; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun struct ept_queue_head { 111*4882a593Smuzhiyun unsigned config; 112*4882a593Smuzhiyun unsigned current; /* read-only */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun unsigned next; 115*4882a593Smuzhiyun unsigned info; 116*4882a593Smuzhiyun unsigned page0; 117*4882a593Smuzhiyun unsigned page1; 118*4882a593Smuzhiyun unsigned page2; 119*4882a593Smuzhiyun unsigned page3; 120*4882a593Smuzhiyun unsigned page4; 121*4882a593Smuzhiyun unsigned reserved_0; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun unsigned char setup_data[8]; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun unsigned reserved_1; 126*4882a593Smuzhiyun unsigned reserved_2; 127*4882a593Smuzhiyun unsigned reserved_3; 128*4882a593Smuzhiyun unsigned reserved_4; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define CONFIG_MAX_PKT(n) ((n) << 16) 132*4882a593Smuzhiyun #define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ 133*4882a593Smuzhiyun #define CONFIG_IOS (1 << 15) /* IRQ on setup */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct ept_queue_item { 136*4882a593Smuzhiyun unsigned next; 137*4882a593Smuzhiyun unsigned info; 138*4882a593Smuzhiyun unsigned page0; 139*4882a593Smuzhiyun unsigned page1; 140*4882a593Smuzhiyun unsigned page2; 141*4882a593Smuzhiyun unsigned page3; 142*4882a593Smuzhiyun unsigned page4; 143*4882a593Smuzhiyun unsigned reserved; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define TERMINATE 1 147*4882a593Smuzhiyun #define INFO_BYTES(n) ((n) << 16) 148*4882a593Smuzhiyun #define INFO_IOC (1 << 15) 149*4882a593Smuzhiyun #define INFO_ACTIVE (1 << 7) 150*4882a593Smuzhiyun #define INFO_HALTED (1 << 6) 151*4882a593Smuzhiyun #define INFO_BUFFER_ERROR (1 << 5) 152*4882a593Smuzhiyun #define INFO_TX_ERROR (1 << 3) 153*4882a593Smuzhiyun #endif 154