1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Broadcom Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <config.h> 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/sysmap.h> 11*4882a593Smuzhiyun #include <asm/kona-common/clk.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "dwc2_udc_otg_priv.h" 14*4882a593Smuzhiyun #include "bcm_udc_otg.h" 15*4882a593Smuzhiyun otg_phy_init(struct dwc2_udc * dev)16*4882a593Smuzhiyunvoid otg_phy_init(struct dwc2_udc *dev) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun /* turn on the USB OTG clocks */ 19*4882a593Smuzhiyun clk_usb_otg_enable((void *)HSOTG_BASE_ADDR); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* set Phy to driving mode */ 22*4882a593Smuzhiyun wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 23*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun udelay(100); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* clear Soft Disconnect */ 28*4882a593Smuzhiyun wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 29*4882a593Smuzhiyun HSOTG_DCTL_SFTDISCON_MASK); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* invoke Reset (active low) */ 32*4882a593Smuzhiyun wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 33*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Reset needs to be asserted for 2ms */ 36*4882a593Smuzhiyun udelay(2000); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* release Reset */ 39*4882a593Smuzhiyun wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 40*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, 41*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun otg_phy_off(struct dwc2_udc * dev)44*4882a593Smuzhiyunvoid otg_phy_off(struct dwc2_udc *dev) 45*4882a593Smuzhiyun { 46*4882a593Smuzhiyun /* Soft Disconnect */ 47*4882a593Smuzhiyun wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 48*4882a593Smuzhiyun HSOTG_DCTL_SFTDISCON_MASK, 49*4882a593Smuzhiyun HSOTG_DCTL_SFTDISCON_MASK); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* set Phy to non-driving (reset) mode */ 52*4882a593Smuzhiyun wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 53*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, 54*4882a593Smuzhiyun HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 55*4882a593Smuzhiyun } 56