1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2004 by Thomas Rathbone, HP Labs 3*4882a593Smuzhiyun * Copyright (C) 2005 by Ivan Kokshaysky 4*4882a593Smuzhiyun * Copyright (C) 2006 by SAN People 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef AT91_UDC_H 10*4882a593Smuzhiyun #define AT91_UDC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * USB Device Port (UDP) registers. 14*4882a593Smuzhiyun * Based on AT91RM9200 datasheet revision E. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */ 18*4882a593Smuzhiyun #define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */ 19*4882a593Smuzhiyun #define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */ 20*4882a593Smuzhiyun #define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define AT91_UDP_GLB_STAT 0x04 /* Global State Register */ 23*4882a593Smuzhiyun #define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */ 24*4882a593Smuzhiyun #define AT91_UDP_CONFG (1 << 1) /* Configured */ 25*4882a593Smuzhiyun #define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */ 26*4882a593Smuzhiyun #define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */ 27*4882a593Smuzhiyun #define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AT91_UDP_FADDR 0x08 /* Function Address Register */ 30*4882a593Smuzhiyun #define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */ 31*4882a593Smuzhiyun #define AT91_UDP_FEN (1 << 8) /* Function Enable */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ 34*4882a593Smuzhiyun #define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ 35*4882a593Smuzhiyun #define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AT91_UDP_ISR 0x1c /* Interrupt Status Register */ 38*4882a593Smuzhiyun #define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */ 39*4882a593Smuzhiyun #define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */ 40*4882a593Smuzhiyun #define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */ 41*4882a593Smuzhiyun #define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status [AT91RM9200 only] */ 42*4882a593Smuzhiyun #define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */ 43*4882a593Smuzhiyun #define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrupt Status */ 44*4882a593Smuzhiyun #define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status [AT91RM9200 only] */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ 47*4882a593Smuzhiyun #define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define AT91_UDP_CSR(n) (0x30+((n)*4)) /* Endpoint Control/Status Registers 0-7 */ 50*4882a593Smuzhiyun #define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */ 51*4882a593Smuzhiyun #define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */ 52*4882a593Smuzhiyun #define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */ 53*4882a593Smuzhiyun #define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */ 54*4882a593Smuzhiyun #define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */ 55*4882a593Smuzhiyun #define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */ 56*4882a593Smuzhiyun #define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */ 57*4882a593Smuzhiyun #define AT91_UDP_DIR (1 << 7) /* Transfer Direction */ 58*4882a593Smuzhiyun #define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */ 59*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_CTRL (0 << 8) 60*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_ISO_OUT (1 << 8) 61*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_BULK_OUT (2 << 8) 62*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_INT_OUT (3 << 8) 63*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_ISO_IN (5 << 8) 64*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_BULK_IN (6 << 8) 65*4882a593Smuzhiyun #define AT91_UDP_EPTYPE_INT_IN (7 << 8) 66*4882a593Smuzhiyun #define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */ 67*4882a593Smuzhiyun #define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */ 68*4882a593Smuzhiyun #define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define AT91_UDP_FDR(n) (0x50+((n)*4)) /* Endpoint FIFO Data Registers 0-7 */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ 73*4882a593Smuzhiyun #define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */ 74*4882a593Smuzhiyun #define AT91_UDP_TXVC_PUON (1 << 9) /* PullUp On [AT91SAM9260 only] */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * controller driver data structures 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define NUM_ENDPOINTS 6 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * hardware won't disable bus reset, or resume while the controller 86*4882a593Smuzhiyun * is suspended ... watching suspend helps keep the logic symmetric. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define MINIMUS_INTERRUPTUS \ 89*4882a593Smuzhiyun (AT91_UDP_ENDBUSRES | AT91_UDP_RXRSM | AT91_UDP_RXSUSP) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct at91_ep { 92*4882a593Smuzhiyun struct usb_ep ep; 93*4882a593Smuzhiyun struct list_head queue; 94*4882a593Smuzhiyun struct at91_udc *udc; 95*4882a593Smuzhiyun void __iomem *creg; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun unsigned maxpacket:16; 98*4882a593Smuzhiyun u8 int_mask; 99*4882a593Smuzhiyun unsigned is_pingpong:1; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun unsigned stopped:1; 102*4882a593Smuzhiyun unsigned is_in:1; 103*4882a593Smuzhiyun unsigned is_iso:1; 104*4882a593Smuzhiyun unsigned fifo_bank:1; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct at91_udc_caps { 108*4882a593Smuzhiyun int (*init)(struct at91_udc *udc); 109*4882a593Smuzhiyun void (*pullup)(struct at91_udc *udc, int is_on); 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * driver is non-SMP, and just blocks IRQs whenever it needs 114*4882a593Smuzhiyun * access protection for chip registers or driver state 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun struct at91_udc { 117*4882a593Smuzhiyun struct usb_gadget gadget; 118*4882a593Smuzhiyun struct at91_ep ep[NUM_ENDPOINTS]; 119*4882a593Smuzhiyun struct usb_gadget_driver *driver; 120*4882a593Smuzhiyun const struct at91_udc_caps *caps; 121*4882a593Smuzhiyun unsigned vbus:1; 122*4882a593Smuzhiyun unsigned enabled:1; 123*4882a593Smuzhiyun unsigned clocked:1; 124*4882a593Smuzhiyun unsigned suspended:1; 125*4882a593Smuzhiyun unsigned req_pending:1; 126*4882a593Smuzhiyun unsigned wait_for_addr_ack:1; 127*4882a593Smuzhiyun unsigned wait_for_config_ack:1; 128*4882a593Smuzhiyun unsigned selfpowered:1; 129*4882a593Smuzhiyun unsigned active_suspend:1; 130*4882a593Smuzhiyun u8 addr; 131*4882a593Smuzhiyun struct at91_udc_data board; 132*4882a593Smuzhiyun void __iomem *udp_baseaddr; 133*4882a593Smuzhiyun int udp_irq; 134*4882a593Smuzhiyun spinlock_t lock; 135*4882a593Smuzhiyun struct at91_matrix *matrix; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun to_udc(struct usb_gadget * g)138*4882a593Smuzhiyunstatic inline struct at91_udc *to_udc(struct usb_gadget *g) 139*4882a593Smuzhiyun { 140*4882a593Smuzhiyun return container_of(g, struct at91_udc, gadget); 141*4882a593Smuzhiyun } 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun struct at91_request { 144*4882a593Smuzhiyun struct usb_request req; 145*4882a593Smuzhiyun struct list_head queue; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #ifdef VERBOSE_DEBUG 151*4882a593Smuzhiyun # define VDBG DBG 152*4882a593Smuzhiyun #else 153*4882a593Smuzhiyun # define VDBG(stuff...) do{}while(0) 154*4882a593Smuzhiyun #endif 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #ifdef PACKET_TRACE 157*4882a593Smuzhiyun # define PACKET VDBG 158*4882a593Smuzhiyun #else 159*4882a593Smuzhiyun # define PACKET(stuff...) do{}while(0) 160*4882a593Smuzhiyun #endif 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define ERR(stuff...) debug("udc: " stuff) 163*4882a593Smuzhiyun #define WARNING(stuff...) debug("udc: " stuff) 164*4882a593Smuzhiyun #define INFO(stuff...) debug("udc: " stuff) 165*4882a593Smuzhiyun #define DBG(stuff...) debug("udc: " stuff) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #endif 168*4882a593Smuzhiyun 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