xref: /OK3568_Linux_fs/u-boot/drivers/usb/eth/smsc95xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2015 Google, Inc
3*4882a593Smuzhiyun  * Copyright (c) 2011 The Chromium OS Authors.
4*4882a593Smuzhiyun  * Copyright (C) 2009 NVIDIA, Corporation
5*4882a593Smuzhiyun  * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <errno.h>
13*4882a593Smuzhiyun #include <malloc.h>
14*4882a593Smuzhiyun #include <memalign.h>
15*4882a593Smuzhiyun #include <usb.h>
16*4882a593Smuzhiyun #include <asm/unaligned.h>
17*4882a593Smuzhiyun #include <linux/mii.h>
18*4882a593Smuzhiyun #include "usb_ether.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* LED defines */
23*4882a593Smuzhiyun #define LED_GPIO_CFG			(0x24)
24*4882a593Smuzhiyun #define LED_GPIO_CFG_SPD_LED		(0x01000000)
25*4882a593Smuzhiyun #define LED_GPIO_CFG_LNK_LED		(0x00100000)
26*4882a593Smuzhiyun #define LED_GPIO_CFG_FDX_LED		(0x00010000)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* Tx command words */
29*4882a593Smuzhiyun #define TX_CMD_A_FIRST_SEG_		0x00002000
30*4882a593Smuzhiyun #define TX_CMD_A_LAST_SEG_		0x00001000
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Rx status word */
33*4882a593Smuzhiyun #define RX_STS_FL_			0x3FFF0000	/* Frame Length */
34*4882a593Smuzhiyun #define RX_STS_ES_			0x00008000	/* Error Summary */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* SCSRs */
37*4882a593Smuzhiyun #define ID_REV				0x00
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define INT_STS				0x08
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define TX_CFG				0x10
42*4882a593Smuzhiyun #define TX_CFG_ON_			0x00000004
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define HW_CFG				0x14
45*4882a593Smuzhiyun #define HW_CFG_BIR_			0x00001000
46*4882a593Smuzhiyun #define HW_CFG_RXDOFF_			0x00000600
47*4882a593Smuzhiyun #define HW_CFG_MEF_			0x00000020
48*4882a593Smuzhiyun #define HW_CFG_BCE_			0x00000002
49*4882a593Smuzhiyun #define HW_CFG_LRST_			0x00000008
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define PM_CTRL				0x20
52*4882a593Smuzhiyun #define PM_CTL_PHY_RST_			0x00000010
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define AFC_CFG				0x2C
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun  * Hi watermark = 15.5Kb (~10 mtu pkts)
58*4882a593Smuzhiyun  * low watermark = 3k (~2 mtu pkts)
59*4882a593Smuzhiyun  * backpressure duration = ~ 350us
60*4882a593Smuzhiyun  * Apply FC on any frame.
61*4882a593Smuzhiyun  */
62*4882a593Smuzhiyun #define AFC_CFG_DEFAULT			0x00F830A1
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define E2P_CMD				0x30
65*4882a593Smuzhiyun #define E2P_CMD_BUSY_			0x80000000
66*4882a593Smuzhiyun #define E2P_CMD_READ_			0x00000000
67*4882a593Smuzhiyun #define E2P_CMD_TIMEOUT_		0x00000400
68*4882a593Smuzhiyun #define E2P_CMD_LOADED_			0x00000200
69*4882a593Smuzhiyun #define E2P_CMD_ADDR_			0x000001FF
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define E2P_DATA			0x34
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define BURST_CAP			0x38
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define INT_EP_CTL			0x68
76*4882a593Smuzhiyun #define INT_EP_CTL_PHY_INT_		0x00008000
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define BULK_IN_DLY			0x6C
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* MAC CSRs */
81*4882a593Smuzhiyun #define MAC_CR				0x100
82*4882a593Smuzhiyun #define MAC_CR_MCPAS_			0x00080000
83*4882a593Smuzhiyun #define MAC_CR_PRMS_			0x00040000
84*4882a593Smuzhiyun #define MAC_CR_HPFILT_			0x00002000
85*4882a593Smuzhiyun #define MAC_CR_TXEN_			0x00000008
86*4882a593Smuzhiyun #define MAC_CR_RXEN_			0x00000004
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define ADDRH				0x104
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define ADDRL				0x108
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define MII_ADDR			0x114
93*4882a593Smuzhiyun #define MII_WRITE_			0x02
94*4882a593Smuzhiyun #define MII_BUSY_			0x01
95*4882a593Smuzhiyun #define MII_READ_			0x00 /* ~of MII Write bit */
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define MII_DATA			0x118
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define FLOW				0x11C
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun #define VLAN1				0x120
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #define COE_CR				0x130
104*4882a593Smuzhiyun #define Tx_COE_EN_			0x00010000
105*4882a593Smuzhiyun #define Rx_COE_EN_			0x00000001
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Vendor-specific PHY Definitions */
108*4882a593Smuzhiyun #define PHY_INT_SRC			29
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define PHY_INT_MASK			30
111*4882a593Smuzhiyun #define PHY_INT_MASK_ANEG_COMP_		((u16)0x0040)
112*4882a593Smuzhiyun #define PHY_INT_MASK_LINK_DOWN_		((u16)0x0010)
113*4882a593Smuzhiyun #define PHY_INT_MASK_DEFAULT_		(PHY_INT_MASK_ANEG_COMP_ | \
114*4882a593Smuzhiyun 					 PHY_INT_MASK_LINK_DOWN_)
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun /* USB Vendor Requests */
117*4882a593Smuzhiyun #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
118*4882a593Smuzhiyun #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* Some extra defines */
121*4882a593Smuzhiyun #define HS_USB_PKT_SIZE			512
122*4882a593Smuzhiyun #define FS_USB_PKT_SIZE			64
123*4882a593Smuzhiyun /* 5/33 is lower limit for BURST_CAP to work */
124*4882a593Smuzhiyun #define DEFAULT_HS_BURST_CAP_SIZE	(5 * HS_USB_PKT_SIZE)
125*4882a593Smuzhiyun #define DEFAULT_FS_BURST_CAP_SIZE	(33 * FS_USB_PKT_SIZE)
126*4882a593Smuzhiyun #define DEFAULT_BULK_IN_DELAY		0x00002000
127*4882a593Smuzhiyun #define MAX_SINGLE_PACKET_SIZE		2048
128*4882a593Smuzhiyun #define EEPROM_MAC_OFFSET		0x01
129*4882a593Smuzhiyun #define SMSC95XX_INTERNAL_PHY_ID	1
130*4882a593Smuzhiyun #define ETH_P_8021Q	0x8100          /* 802.1Q VLAN Extended Header  */
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* local defines */
133*4882a593Smuzhiyun #define SMSC95XX_BASE_NAME "sms"
134*4882a593Smuzhiyun #define USB_CTRL_SET_TIMEOUT 5000
135*4882a593Smuzhiyun #define USB_CTRL_GET_TIMEOUT 5000
136*4882a593Smuzhiyun #define USB_BULK_SEND_TIMEOUT 5000
137*4882a593Smuzhiyun #define USB_BULK_RECV_TIMEOUT 5000
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
140*4882a593Smuzhiyun #define PHY_CONNECT_TIMEOUT 5000
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define TURBO_MODE
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun #ifndef CONFIG_DM_ETH
145*4882a593Smuzhiyun /* local vars */
146*4882a593Smuzhiyun static int curr_eth_dev; /* index for name of next device detected */
147*4882a593Smuzhiyun #endif
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun /* driver private */
150*4882a593Smuzhiyun struct smsc95xx_private {
151*4882a593Smuzhiyun #ifdef CONFIG_DM_ETH
152*4882a593Smuzhiyun 	struct ueth_data ueth;
153*4882a593Smuzhiyun #endif
154*4882a593Smuzhiyun 	size_t rx_urb_size;  /* maximum USB URB size */
155*4882a593Smuzhiyun 	u32 mac_cr;  /* MAC control register value */
156*4882a593Smuzhiyun 	int have_hwaddr;  /* 1 if we have a hardware MAC address */
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun  * Smsc95xx infrastructure commands
161*4882a593Smuzhiyun  */
smsc95xx_write_reg(struct usb_device * udev,u32 index,u32 data)162*4882a593Smuzhiyun static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	int len;
165*4882a593Smuzhiyun 	ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	cpu_to_le32s(&data);
168*4882a593Smuzhiyun 	tmpbuf[0] = data;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
171*4882a593Smuzhiyun 			      USB_VENDOR_REQUEST_WRITE_REGISTER,
172*4882a593Smuzhiyun 			      USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
173*4882a593Smuzhiyun 			      0, index, tmpbuf, sizeof(data),
174*4882a593Smuzhiyun 			      USB_CTRL_SET_TIMEOUT);
175*4882a593Smuzhiyun 	if (len != sizeof(data)) {
176*4882a593Smuzhiyun 		debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
177*4882a593Smuzhiyun 		      index, data, len);
178*4882a593Smuzhiyun 		return -EIO;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 	return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
smsc95xx_read_reg(struct usb_device * udev,u32 index,u32 * data)183*4882a593Smuzhiyun static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	int len;
186*4882a593Smuzhiyun 	ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
189*4882a593Smuzhiyun 			      USB_VENDOR_REQUEST_READ_REGISTER,
190*4882a593Smuzhiyun 			      USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
191*4882a593Smuzhiyun 			      0, index, tmpbuf, sizeof(*data),
192*4882a593Smuzhiyun 			      USB_CTRL_GET_TIMEOUT);
193*4882a593Smuzhiyun 	*data = tmpbuf[0];
194*4882a593Smuzhiyun 	if (len != sizeof(*data)) {
195*4882a593Smuzhiyun 		debug("smsc95xx_read_reg failed: index=%d, len=%d",
196*4882a593Smuzhiyun 		      index, len);
197*4882a593Smuzhiyun 		return -EIO;
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	le32_to_cpus(data);
201*4882a593Smuzhiyun 	return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /* Loop until the read is completed with timeout */
smsc95xx_phy_wait_not_busy(struct usb_device * udev)205*4882a593Smuzhiyun static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	unsigned long start_time = get_timer(0);
208*4882a593Smuzhiyun 	u32 val;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	do {
211*4882a593Smuzhiyun 		smsc95xx_read_reg(udev, MII_ADDR, &val);
212*4882a593Smuzhiyun 		if (!(val & MII_BUSY_))
213*4882a593Smuzhiyun 			return 0;
214*4882a593Smuzhiyun 	} while (get_timer(start_time) < 1000);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	return -ETIMEDOUT;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
smsc95xx_mdio_read(struct usb_device * udev,int phy_id,int idx)219*4882a593Smuzhiyun static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun 	u32 val, addr;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/* confirm MII not busy */
224*4882a593Smuzhiyun 	if (smsc95xx_phy_wait_not_busy(udev)) {
225*4882a593Smuzhiyun 		debug("MII is busy in smsc95xx_mdio_read\n");
226*4882a593Smuzhiyun 		return -ETIMEDOUT;
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	/* set the address, index & direction (read from PHY) */
230*4882a593Smuzhiyun 	addr = (phy_id << 11) | (idx << 6) | MII_READ_;
231*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, MII_ADDR, addr);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	if (smsc95xx_phy_wait_not_busy(udev)) {
234*4882a593Smuzhiyun 		debug("Timed out reading MII reg %02X\n", idx);
235*4882a593Smuzhiyun 		return -ETIMEDOUT;
236*4882a593Smuzhiyun 	}
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	smsc95xx_read_reg(udev, MII_DATA, &val);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	return (u16)(val & 0xFFFF);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
smsc95xx_mdio_write(struct usb_device * udev,int phy_id,int idx,int regval)243*4882a593Smuzhiyun static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
244*4882a593Smuzhiyun 				int regval)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	u32 val, addr;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	/* confirm MII not busy */
249*4882a593Smuzhiyun 	if (smsc95xx_phy_wait_not_busy(udev)) {
250*4882a593Smuzhiyun 		debug("MII is busy in smsc95xx_mdio_write\n");
251*4882a593Smuzhiyun 		return;
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	val = regval;
255*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, MII_DATA, val);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/* set the address, index & direction (write to PHY) */
258*4882a593Smuzhiyun 	addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
259*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, MII_ADDR, addr);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	if (smsc95xx_phy_wait_not_busy(udev))
262*4882a593Smuzhiyun 		debug("Timed out writing MII reg %02X\n", idx);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
smsc95xx_eeprom_confirm_not_busy(struct usb_device * udev)265*4882a593Smuzhiyun static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	unsigned long start_time = get_timer(0);
268*4882a593Smuzhiyun 	u32 val;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	do {
271*4882a593Smuzhiyun 		smsc95xx_read_reg(udev, E2P_CMD, &val);
272*4882a593Smuzhiyun 		if (!(val & E2P_CMD_BUSY_))
273*4882a593Smuzhiyun 			return 0;
274*4882a593Smuzhiyun 		udelay(40);
275*4882a593Smuzhiyun 	} while (get_timer(start_time) < 1 * 1000 * 1000);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	debug("EEPROM is busy\n");
278*4882a593Smuzhiyun 	return -ETIMEDOUT;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun 
smsc95xx_wait_eeprom(struct usb_device * udev)281*4882a593Smuzhiyun static int smsc95xx_wait_eeprom(struct usb_device *udev)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun 	unsigned long start_time = get_timer(0);
284*4882a593Smuzhiyun 	u32 val;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	do {
287*4882a593Smuzhiyun 		smsc95xx_read_reg(udev, E2P_CMD, &val);
288*4882a593Smuzhiyun 		if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
289*4882a593Smuzhiyun 			break;
290*4882a593Smuzhiyun 		udelay(40);
291*4882a593Smuzhiyun 	} while (get_timer(start_time) < 1 * 1000 * 1000);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
294*4882a593Smuzhiyun 		debug("EEPROM read operation timeout\n");
295*4882a593Smuzhiyun 		return -ETIMEDOUT;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 	return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
smsc95xx_read_eeprom(struct usb_device * udev,u32 offset,u32 length,u8 * data)300*4882a593Smuzhiyun static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
301*4882a593Smuzhiyun 				u8 *data)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	u32 val;
304*4882a593Smuzhiyun 	int i, ret;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	ret = smsc95xx_eeprom_confirm_not_busy(udev);
307*4882a593Smuzhiyun 	if (ret)
308*4882a593Smuzhiyun 		return ret;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	for (i = 0; i < length; i++) {
311*4882a593Smuzhiyun 		val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
312*4882a593Smuzhiyun 		smsc95xx_write_reg(udev, E2P_CMD, val);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 		ret = smsc95xx_wait_eeprom(udev);
315*4882a593Smuzhiyun 		if (ret < 0)
316*4882a593Smuzhiyun 			return ret;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 		smsc95xx_read_reg(udev, E2P_DATA, &val);
319*4882a593Smuzhiyun 		data[i] = val & 0xFF;
320*4882a593Smuzhiyun 		offset++;
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 	return 0;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun /*
326*4882a593Smuzhiyun  * mii_nway_restart - restart NWay (autonegotiation) for this interface
327*4882a593Smuzhiyun  *
328*4882a593Smuzhiyun  * Returns 0 on success, negative on error.
329*4882a593Smuzhiyun  */
mii_nway_restart(struct usb_device * udev,struct ueth_data * dev)330*4882a593Smuzhiyun static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	int bmcr;
333*4882a593Smuzhiyun 	int r = -1;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	/* if autoneg is off, it's an error */
336*4882a593Smuzhiyun 	bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	if (bmcr & BMCR_ANENABLE) {
339*4882a593Smuzhiyun 		bmcr |= BMCR_ANRESTART;
340*4882a593Smuzhiyun 		smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
341*4882a593Smuzhiyun 		r = 0;
342*4882a593Smuzhiyun 	}
343*4882a593Smuzhiyun 	return r;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
smsc95xx_phy_initialize(struct usb_device * udev,struct ueth_data * dev)346*4882a593Smuzhiyun static int smsc95xx_phy_initialize(struct usb_device *udev,
347*4882a593Smuzhiyun 				   struct ueth_data *dev)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
350*4882a593Smuzhiyun 	smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
351*4882a593Smuzhiyun 			    ADVERTISE_ALL | ADVERTISE_CSMA |
352*4882a593Smuzhiyun 			    ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	/* read to clear */
355*4882a593Smuzhiyun 	smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
358*4882a593Smuzhiyun 			    PHY_INT_MASK_DEFAULT_);
359*4882a593Smuzhiyun 	mii_nway_restart(udev, dev);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	debug("phy initialised succesfully\n");
362*4882a593Smuzhiyun 	return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
smsc95xx_init_mac_address(unsigned char * enetaddr,struct usb_device * udev)365*4882a593Smuzhiyun static int smsc95xx_init_mac_address(unsigned char *enetaddr,
366*4882a593Smuzhiyun 				     struct usb_device *udev)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun 	int ret;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	/* try reading mac address from EEPROM */
371*4882a593Smuzhiyun 	ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
372*4882a593Smuzhiyun 	if (ret)
373*4882a593Smuzhiyun 		return ret;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	if (is_valid_ethaddr(enetaddr)) {
376*4882a593Smuzhiyun 		/* eeprom values are valid so use them */
377*4882a593Smuzhiyun 		debug("MAC address read from EEPROM\n");
378*4882a593Smuzhiyun 		return 0;
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	/*
382*4882a593Smuzhiyun 	 * No eeprom, or eeprom values are invalid. Generating a random MAC
383*4882a593Smuzhiyun 	 * address is not safe. Just return an error.
384*4882a593Smuzhiyun 	 */
385*4882a593Smuzhiyun 	debug("Invalid MAC address read from EEPROM\n");
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	return -ENXIO;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
smsc95xx_write_hwaddr_common(struct usb_device * udev,struct smsc95xx_private * priv,unsigned char * enetaddr)390*4882a593Smuzhiyun static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
391*4882a593Smuzhiyun 					struct smsc95xx_private *priv,
392*4882a593Smuzhiyun 					unsigned char *enetaddr)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
395*4882a593Smuzhiyun 	u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
396*4882a593Smuzhiyun 	int ret;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	/* set hardware address */
399*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
400*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
401*4882a593Smuzhiyun 	if (ret < 0)
402*4882a593Smuzhiyun 		return ret;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
405*4882a593Smuzhiyun 	if (ret < 0)
406*4882a593Smuzhiyun 		return ret;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	debug("MAC %pM\n", enetaddr);
409*4882a593Smuzhiyun 	priv->have_hwaddr = 1;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	return 0;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun /* Enable or disable Tx & Rx checksum offload engines */
smsc95xx_set_csums(struct usb_device * udev,int use_tx_csum,int use_rx_csum)415*4882a593Smuzhiyun static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
416*4882a593Smuzhiyun 			      int use_rx_csum)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun 	u32 read_buf;
419*4882a593Smuzhiyun 	int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
420*4882a593Smuzhiyun 	if (ret < 0)
421*4882a593Smuzhiyun 		return ret;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (use_tx_csum)
424*4882a593Smuzhiyun 		read_buf |= Tx_COE_EN_;
425*4882a593Smuzhiyun 	else
426*4882a593Smuzhiyun 		read_buf &= ~Tx_COE_EN_;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	if (use_rx_csum)
429*4882a593Smuzhiyun 		read_buf |= Rx_COE_EN_;
430*4882a593Smuzhiyun 	else
431*4882a593Smuzhiyun 		read_buf &= ~Rx_COE_EN_;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
434*4882a593Smuzhiyun 	if (ret < 0)
435*4882a593Smuzhiyun 		return ret;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	debug("COE_CR = 0x%08x\n", read_buf);
438*4882a593Smuzhiyun 	return 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun 
smsc95xx_set_multicast(struct smsc95xx_private * priv)441*4882a593Smuzhiyun static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun 	/* No multicast in u-boot */
444*4882a593Smuzhiyun 	priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun /* starts the TX path */
smsc95xx_start_tx_path(struct usb_device * udev,struct smsc95xx_private * priv)448*4882a593Smuzhiyun static void smsc95xx_start_tx_path(struct usb_device *udev,
449*4882a593Smuzhiyun 				   struct smsc95xx_private *priv)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	u32 reg_val;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	/* Enable Tx at MAC */
454*4882a593Smuzhiyun 	priv->mac_cr |= MAC_CR_TXEN_;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	/* Enable Tx at SCSRs */
459*4882a593Smuzhiyun 	reg_val = TX_CFG_ON_;
460*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, TX_CFG, reg_val);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun /* Starts the Receive path */
smsc95xx_start_rx_path(struct usb_device * udev,struct smsc95xx_private * priv)464*4882a593Smuzhiyun static void smsc95xx_start_rx_path(struct usb_device *udev,
465*4882a593Smuzhiyun 				   struct smsc95xx_private *priv)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	priv->mac_cr |= MAC_CR_RXEN_;
468*4882a593Smuzhiyun 	smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
smsc95xx_init_common(struct usb_device * udev,struct ueth_data * dev,struct smsc95xx_private * priv,unsigned char * enetaddr)471*4882a593Smuzhiyun static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
472*4882a593Smuzhiyun 				struct smsc95xx_private *priv,
473*4882a593Smuzhiyun 				unsigned char *enetaddr)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun 	int ret;
476*4882a593Smuzhiyun 	u32 write_buf;
477*4882a593Smuzhiyun 	u32 read_buf;
478*4882a593Smuzhiyun 	u32 burst_cap;
479*4882a593Smuzhiyun 	int timeout;
480*4882a593Smuzhiyun #define TIMEOUT_RESOLUTION 50	/* ms */
481*4882a593Smuzhiyun 	int link_detected;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
484*4882a593Smuzhiyun 	dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	write_buf = HW_CFG_LRST_;
487*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
488*4882a593Smuzhiyun 	if (ret < 0)
489*4882a593Smuzhiyun 		return ret;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	timeout = 0;
492*4882a593Smuzhiyun 	do {
493*4882a593Smuzhiyun 		ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
494*4882a593Smuzhiyun 		if (ret < 0)
495*4882a593Smuzhiyun 			return ret;
496*4882a593Smuzhiyun 		udelay(10 * 1000);
497*4882a593Smuzhiyun 		timeout++;
498*4882a593Smuzhiyun 	} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	if (timeout >= 100) {
501*4882a593Smuzhiyun 		debug("timeout waiting for completion of Lite Reset\n");
502*4882a593Smuzhiyun 		return -ETIMEDOUT;
503*4882a593Smuzhiyun 	}
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	write_buf = PM_CTL_PHY_RST_;
506*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
507*4882a593Smuzhiyun 	if (ret < 0)
508*4882a593Smuzhiyun 		return ret;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	timeout = 0;
511*4882a593Smuzhiyun 	do {
512*4882a593Smuzhiyun 		ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
513*4882a593Smuzhiyun 		if (ret < 0)
514*4882a593Smuzhiyun 			return ret;
515*4882a593Smuzhiyun 		udelay(10 * 1000);
516*4882a593Smuzhiyun 		timeout++;
517*4882a593Smuzhiyun 	} while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
518*4882a593Smuzhiyun 	if (timeout >= 100) {
519*4882a593Smuzhiyun 		debug("timeout waiting for PHY Reset\n");
520*4882a593Smuzhiyun 		return -ETIMEDOUT;
521*4882a593Smuzhiyun 	}
522*4882a593Smuzhiyun #ifndef CONFIG_DM_ETH
523*4882a593Smuzhiyun 	if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
524*4882a593Smuzhiyun 			0)
525*4882a593Smuzhiyun 		priv->have_hwaddr = 1;
526*4882a593Smuzhiyun #endif
527*4882a593Smuzhiyun 	if (!priv->have_hwaddr) {
528*4882a593Smuzhiyun 		puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
529*4882a593Smuzhiyun 		return -EADDRNOTAVAIL;
530*4882a593Smuzhiyun 	}
531*4882a593Smuzhiyun 	ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
532*4882a593Smuzhiyun 	if (ret < 0)
533*4882a593Smuzhiyun 		return ret;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun #ifdef TURBO_MODE
536*4882a593Smuzhiyun 	if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
537*4882a593Smuzhiyun 		burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
538*4882a593Smuzhiyun 		priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
539*4882a593Smuzhiyun 	} else {
540*4882a593Smuzhiyun 		burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
541*4882a593Smuzhiyun 		priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
542*4882a593Smuzhiyun 	}
543*4882a593Smuzhiyun #else
544*4882a593Smuzhiyun 	burst_cap = 0;
545*4882a593Smuzhiyun 	priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
546*4882a593Smuzhiyun #endif
547*4882a593Smuzhiyun 	debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
550*4882a593Smuzhiyun 	if (ret < 0)
551*4882a593Smuzhiyun 		return ret;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
554*4882a593Smuzhiyun 	if (ret < 0)
555*4882a593Smuzhiyun 		return ret;
556*4882a593Smuzhiyun 	debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	read_buf = DEFAULT_BULK_IN_DELAY;
559*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
560*4882a593Smuzhiyun 	if (ret < 0)
561*4882a593Smuzhiyun 		return ret;
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
564*4882a593Smuzhiyun 	if (ret < 0)
565*4882a593Smuzhiyun 		return ret;
566*4882a593Smuzhiyun 	debug("Read Value from BULK_IN_DLY after writing: "
567*4882a593Smuzhiyun 			"0x%08x\n", read_buf);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
570*4882a593Smuzhiyun 	if (ret < 0)
571*4882a593Smuzhiyun 		return ret;
572*4882a593Smuzhiyun 	debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun #ifdef TURBO_MODE
575*4882a593Smuzhiyun 	read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
576*4882a593Smuzhiyun #endif
577*4882a593Smuzhiyun 	read_buf &= ~HW_CFG_RXDOFF_;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun #define NET_IP_ALIGN 0
580*4882a593Smuzhiyun 	read_buf |= NET_IP_ALIGN << 9;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
583*4882a593Smuzhiyun 	if (ret < 0)
584*4882a593Smuzhiyun 		return ret;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
587*4882a593Smuzhiyun 	if (ret < 0)
588*4882a593Smuzhiyun 		return ret;
589*4882a593Smuzhiyun 	debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	write_buf = 0xFFFFFFFF;
592*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
593*4882a593Smuzhiyun 	if (ret < 0)
594*4882a593Smuzhiyun 		return ret;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
597*4882a593Smuzhiyun 	if (ret < 0)
598*4882a593Smuzhiyun 		return ret;
599*4882a593Smuzhiyun 	debug("ID_REV = 0x%08x\n", read_buf);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/* Configure GPIO pins as LED outputs */
602*4882a593Smuzhiyun 	write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
603*4882a593Smuzhiyun 		LED_GPIO_CFG_FDX_LED;
604*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
605*4882a593Smuzhiyun 	if (ret < 0)
606*4882a593Smuzhiyun 		return ret;
607*4882a593Smuzhiyun 	debug("LED_GPIO_CFG set\n");
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	/* Init Tx */
610*4882a593Smuzhiyun 	write_buf = 0;
611*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, FLOW, write_buf);
612*4882a593Smuzhiyun 	if (ret < 0)
613*4882a593Smuzhiyun 		return ret;
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	read_buf = AFC_CFG_DEFAULT;
616*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
617*4882a593Smuzhiyun 	if (ret < 0)
618*4882a593Smuzhiyun 		return ret;
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
621*4882a593Smuzhiyun 	if (ret < 0)
622*4882a593Smuzhiyun 		return ret;
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	/* Init Rx. Set Vlan */
625*4882a593Smuzhiyun 	write_buf = (u32)ETH_P_8021Q;
626*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
627*4882a593Smuzhiyun 	if (ret < 0)
628*4882a593Smuzhiyun 		return ret;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	/* Disable checksum offload engines */
631*4882a593Smuzhiyun 	ret = smsc95xx_set_csums(udev, 0, 0);
632*4882a593Smuzhiyun 	if (ret < 0) {
633*4882a593Smuzhiyun 		debug("Failed to set csum offload: %d\n", ret);
634*4882a593Smuzhiyun 		return ret;
635*4882a593Smuzhiyun 	}
636*4882a593Smuzhiyun 	smsc95xx_set_multicast(priv);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	ret = smsc95xx_phy_initialize(udev, dev);
639*4882a593Smuzhiyun 	if (ret < 0)
640*4882a593Smuzhiyun 		return ret;
641*4882a593Smuzhiyun 	ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
642*4882a593Smuzhiyun 	if (ret < 0)
643*4882a593Smuzhiyun 		return ret;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	/* enable PHY interrupts */
646*4882a593Smuzhiyun 	read_buf |= INT_EP_CTL_PHY_INT_;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
649*4882a593Smuzhiyun 	if (ret < 0)
650*4882a593Smuzhiyun 		return ret;
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	smsc95xx_start_tx_path(udev, priv);
653*4882a593Smuzhiyun 	smsc95xx_start_rx_path(udev, priv);
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	timeout = 0;
656*4882a593Smuzhiyun 	do {
657*4882a593Smuzhiyun 		link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
658*4882a593Smuzhiyun 			& BMSR_LSTATUS;
659*4882a593Smuzhiyun 		if (!link_detected) {
660*4882a593Smuzhiyun 			if (timeout == 0)
661*4882a593Smuzhiyun 				printf("Waiting for Ethernet connection... ");
662*4882a593Smuzhiyun 			udelay(TIMEOUT_RESOLUTION * 1000);
663*4882a593Smuzhiyun 			timeout += TIMEOUT_RESOLUTION;
664*4882a593Smuzhiyun 		}
665*4882a593Smuzhiyun 	} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
666*4882a593Smuzhiyun 	if (link_detected) {
667*4882a593Smuzhiyun 		if (timeout != 0)
668*4882a593Smuzhiyun 			printf("done.\n");
669*4882a593Smuzhiyun 	} else {
670*4882a593Smuzhiyun 		printf("unable to connect.\n");
671*4882a593Smuzhiyun 		return -EIO;
672*4882a593Smuzhiyun 	}
673*4882a593Smuzhiyun 	return 0;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
smsc95xx_send_common(struct ueth_data * dev,void * packet,int length)676*4882a593Smuzhiyun static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun 	int err;
679*4882a593Smuzhiyun 	int actual_len;
680*4882a593Smuzhiyun 	u32 tx_cmd_a;
681*4882a593Smuzhiyun 	u32 tx_cmd_b;
682*4882a593Smuzhiyun 	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
683*4882a593Smuzhiyun 				 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	debug("** %s(), len %d, buf %#x\n", __func__, length,
686*4882a593Smuzhiyun 	      (unsigned int)(ulong)msg);
687*4882a593Smuzhiyun 	if (length > PKTSIZE)
688*4882a593Smuzhiyun 		return -ENOSPC;
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
691*4882a593Smuzhiyun 	tx_cmd_b = (u32)length;
692*4882a593Smuzhiyun 	cpu_to_le32s(&tx_cmd_a);
693*4882a593Smuzhiyun 	cpu_to_le32s(&tx_cmd_b);
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	/* prepend cmd_a and cmd_b */
696*4882a593Smuzhiyun 	memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
697*4882a593Smuzhiyun 	memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
698*4882a593Smuzhiyun 	memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
699*4882a593Smuzhiyun 	       length);
700*4882a593Smuzhiyun 	err = usb_bulk_msg(dev->pusb_dev,
701*4882a593Smuzhiyun 				usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
702*4882a593Smuzhiyun 				(void *)msg,
703*4882a593Smuzhiyun 				length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
704*4882a593Smuzhiyun 				&actual_len,
705*4882a593Smuzhiyun 				USB_BULK_SEND_TIMEOUT);
706*4882a593Smuzhiyun 	debug("Tx: len = %u, actual = %u, err = %d\n",
707*4882a593Smuzhiyun 	      (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
708*4882a593Smuzhiyun 	      (unsigned int)actual_len, err);
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	return err;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun #ifndef CONFIG_DM_ETH
714*4882a593Smuzhiyun /*
715*4882a593Smuzhiyun  * Smsc95xx callbacks
716*4882a593Smuzhiyun  */
smsc95xx_init(struct eth_device * eth,bd_t * bd)717*4882a593Smuzhiyun static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
718*4882a593Smuzhiyun {
719*4882a593Smuzhiyun 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
720*4882a593Smuzhiyun 	struct usb_device *udev = dev->pusb_dev;
721*4882a593Smuzhiyun 	struct smsc95xx_private *priv =
722*4882a593Smuzhiyun 		(struct smsc95xx_private *)dev->dev_priv;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun 
smsc95xx_send(struct eth_device * eth,void * packet,int length)727*4882a593Smuzhiyun static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	return smsc95xx_send_common(dev, packet, length);
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun 
smsc95xx_recv(struct eth_device * eth)734*4882a593Smuzhiyun static int smsc95xx_recv(struct eth_device *eth)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
737*4882a593Smuzhiyun 	DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
738*4882a593Smuzhiyun 	unsigned char *buf_ptr;
739*4882a593Smuzhiyun 	int err;
740*4882a593Smuzhiyun 	int actual_len;
741*4882a593Smuzhiyun 	u32 packet_len;
742*4882a593Smuzhiyun 	int cur_buf_align;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
745*4882a593Smuzhiyun 	err = usb_bulk_msg(dev->pusb_dev,
746*4882a593Smuzhiyun 			   usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
747*4882a593Smuzhiyun 			   (void *)recv_buf, RX_URB_SIZE, &actual_len,
748*4882a593Smuzhiyun 			   USB_BULK_RECV_TIMEOUT);
749*4882a593Smuzhiyun 	debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
750*4882a593Smuzhiyun 	      actual_len, err);
751*4882a593Smuzhiyun 	if (err != 0) {
752*4882a593Smuzhiyun 		debug("Rx: failed to receive\n");
753*4882a593Smuzhiyun 		return -err;
754*4882a593Smuzhiyun 	}
755*4882a593Smuzhiyun 	if (actual_len > RX_URB_SIZE) {
756*4882a593Smuzhiyun 		debug("Rx: received too many bytes %d\n", actual_len);
757*4882a593Smuzhiyun 		return -ENOSPC;
758*4882a593Smuzhiyun 	}
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	buf_ptr = recv_buf;
761*4882a593Smuzhiyun 	while (actual_len > 0) {
762*4882a593Smuzhiyun 		/*
763*4882a593Smuzhiyun 		 * 1st 4 bytes contain the length of the actual data plus error
764*4882a593Smuzhiyun 		 * info. Extract data length.
765*4882a593Smuzhiyun 		 */
766*4882a593Smuzhiyun 		if (actual_len < sizeof(packet_len)) {
767*4882a593Smuzhiyun 			debug("Rx: incomplete packet length\n");
768*4882a593Smuzhiyun 			return -EIO;
769*4882a593Smuzhiyun 		}
770*4882a593Smuzhiyun 		memcpy(&packet_len, buf_ptr, sizeof(packet_len));
771*4882a593Smuzhiyun 		le32_to_cpus(&packet_len);
772*4882a593Smuzhiyun 		if (packet_len & RX_STS_ES_) {
773*4882a593Smuzhiyun 			debug("Rx: Error header=%#x", packet_len);
774*4882a593Smuzhiyun 			return -EIO;
775*4882a593Smuzhiyun 		}
776*4882a593Smuzhiyun 		packet_len = ((packet_len & RX_STS_FL_) >> 16);
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 		if (packet_len > actual_len - sizeof(packet_len)) {
779*4882a593Smuzhiyun 			debug("Rx: too large packet: %d\n", packet_len);
780*4882a593Smuzhiyun 			return -EIO;
781*4882a593Smuzhiyun 		}
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 		/* Notify net stack */
784*4882a593Smuzhiyun 		net_process_received_packet(buf_ptr + sizeof(packet_len),
785*4882a593Smuzhiyun 					    packet_len - 4);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 		/* Adjust for next iteration */
788*4882a593Smuzhiyun 		actual_len -= sizeof(packet_len) + packet_len;
789*4882a593Smuzhiyun 		buf_ptr += sizeof(packet_len) + packet_len;
790*4882a593Smuzhiyun 		cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 		if (cur_buf_align & 0x03) {
793*4882a593Smuzhiyun 			int align = 4 - (cur_buf_align & 0x03);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 			actual_len -= align;
796*4882a593Smuzhiyun 			buf_ptr += align;
797*4882a593Smuzhiyun 		}
798*4882a593Smuzhiyun 	}
799*4882a593Smuzhiyun 	return err;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun 
smsc95xx_halt(struct eth_device * eth)802*4882a593Smuzhiyun static void smsc95xx_halt(struct eth_device *eth)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun 
smsc95xx_write_hwaddr(struct eth_device * eth)807*4882a593Smuzhiyun static int smsc95xx_write_hwaddr(struct eth_device *eth)
808*4882a593Smuzhiyun {
809*4882a593Smuzhiyun 	struct ueth_data *dev = eth->priv;
810*4882a593Smuzhiyun 	struct usb_device *udev = dev->pusb_dev;
811*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev->dev_priv;
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun /*
817*4882a593Smuzhiyun  * SMSC probing functions
818*4882a593Smuzhiyun  */
smsc95xx_eth_before_probe(void)819*4882a593Smuzhiyun void smsc95xx_eth_before_probe(void)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun 	curr_eth_dev = 0;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun struct smsc95xx_dongle {
825*4882a593Smuzhiyun 	unsigned short vendor;
826*4882a593Smuzhiyun 	unsigned short product;
827*4882a593Smuzhiyun };
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun static const struct smsc95xx_dongle smsc95xx_dongles[] = {
830*4882a593Smuzhiyun 	{ 0x0424, 0xec00 },	/* LAN9512/LAN9514 Ethernet */
831*4882a593Smuzhiyun 	{ 0x0424, 0x9500 },	/* LAN9500 Ethernet */
832*4882a593Smuzhiyun 	{ 0x0424, 0x9730 },	/* LAN9730 Ethernet (HSIC) */
833*4882a593Smuzhiyun 	{ 0x0424, 0x9900 },	/* SMSC9500 USB Ethernet Device (SAL10) */
834*4882a593Smuzhiyun 	{ 0x0424, 0x9e00 },	/* LAN9500A Ethernet */
835*4882a593Smuzhiyun 	{ 0x0000, 0x0000 }	/* END - Do not remove */
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun /* Probe to see if a new device is actually an SMSC device */
smsc95xx_eth_probe(struct usb_device * dev,unsigned int ifnum,struct ueth_data * ss)839*4882a593Smuzhiyun int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
840*4882a593Smuzhiyun 		      struct ueth_data *ss)
841*4882a593Smuzhiyun {
842*4882a593Smuzhiyun 	struct usb_interface *iface;
843*4882a593Smuzhiyun 	struct usb_interface_descriptor *iface_desc;
844*4882a593Smuzhiyun 	int i;
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 	/* let's examine the device now */
847*4882a593Smuzhiyun 	iface = &dev->config.if_desc[ifnum];
848*4882a593Smuzhiyun 	iface_desc = &dev->config.if_desc[ifnum].desc;
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
851*4882a593Smuzhiyun 		if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
852*4882a593Smuzhiyun 		    dev->descriptor.idProduct == smsc95xx_dongles[i].product)
853*4882a593Smuzhiyun 			/* Found a supported dongle */
854*4882a593Smuzhiyun 			break;
855*4882a593Smuzhiyun 	}
856*4882a593Smuzhiyun 	if (smsc95xx_dongles[i].vendor == 0)
857*4882a593Smuzhiyun 		return 0;
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	/* At this point, we know we've got a live one */
860*4882a593Smuzhiyun 	debug("\n\nUSB Ethernet device detected\n");
861*4882a593Smuzhiyun 	memset(ss, '\0', sizeof(struct ueth_data));
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	/* Initialize the ueth_data structure with some useful info */
864*4882a593Smuzhiyun 	ss->ifnum = ifnum;
865*4882a593Smuzhiyun 	ss->pusb_dev = dev;
866*4882a593Smuzhiyun 	ss->subclass = iface_desc->bInterfaceSubClass;
867*4882a593Smuzhiyun 	ss->protocol = iface_desc->bInterfaceProtocol;
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun 	/*
870*4882a593Smuzhiyun 	 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
871*4882a593Smuzhiyun 	 * We will ignore any others.
872*4882a593Smuzhiyun 	 */
873*4882a593Smuzhiyun 	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
874*4882a593Smuzhiyun 		/* is it an BULK endpoint? */
875*4882a593Smuzhiyun 		if ((iface->ep_desc[i].bmAttributes &
876*4882a593Smuzhiyun 		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
877*4882a593Smuzhiyun 			if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
878*4882a593Smuzhiyun 				ss->ep_in =
879*4882a593Smuzhiyun 					iface->ep_desc[i].bEndpointAddress &
880*4882a593Smuzhiyun 					USB_ENDPOINT_NUMBER_MASK;
881*4882a593Smuzhiyun 			else
882*4882a593Smuzhiyun 				ss->ep_out =
883*4882a593Smuzhiyun 					iface->ep_desc[i].bEndpointAddress &
884*4882a593Smuzhiyun 					USB_ENDPOINT_NUMBER_MASK;
885*4882a593Smuzhiyun 		}
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 		/* is it an interrupt endpoint? */
888*4882a593Smuzhiyun 		if ((iface->ep_desc[i].bmAttributes &
889*4882a593Smuzhiyun 		    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
890*4882a593Smuzhiyun 			ss->ep_int = iface->ep_desc[i].bEndpointAddress &
891*4882a593Smuzhiyun 				USB_ENDPOINT_NUMBER_MASK;
892*4882a593Smuzhiyun 			ss->irqinterval = iface->ep_desc[i].bInterval;
893*4882a593Smuzhiyun 		}
894*4882a593Smuzhiyun 	}
895*4882a593Smuzhiyun 	debug("Endpoints In %d Out %d Int %d\n",
896*4882a593Smuzhiyun 		  ss->ep_in, ss->ep_out, ss->ep_int);
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 	/* Do some basic sanity checks, and bail if we find a problem */
899*4882a593Smuzhiyun 	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
900*4882a593Smuzhiyun 	    !ss->ep_in || !ss->ep_out || !ss->ep_int) {
901*4882a593Smuzhiyun 		debug("Problems with device\n");
902*4882a593Smuzhiyun 		return 0;
903*4882a593Smuzhiyun 	}
904*4882a593Smuzhiyun 	dev->privptr = (void *)ss;
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 	/* alloc driver private */
907*4882a593Smuzhiyun 	ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
908*4882a593Smuzhiyun 	if (!ss->dev_priv)
909*4882a593Smuzhiyun 		return 0;
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	return 1;
912*4882a593Smuzhiyun }
913*4882a593Smuzhiyun 
smsc95xx_eth_get_info(struct usb_device * dev,struct ueth_data * ss,struct eth_device * eth)914*4882a593Smuzhiyun int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
915*4882a593Smuzhiyun 				struct eth_device *eth)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
918*4882a593Smuzhiyun 	if (!eth) {
919*4882a593Smuzhiyun 		debug("%s: missing parameter.\n", __func__);
920*4882a593Smuzhiyun 		return 0;
921*4882a593Smuzhiyun 	}
922*4882a593Smuzhiyun 	sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
923*4882a593Smuzhiyun 	eth->init = smsc95xx_init;
924*4882a593Smuzhiyun 	eth->send = smsc95xx_send;
925*4882a593Smuzhiyun 	eth->recv = smsc95xx_recv;
926*4882a593Smuzhiyun 	eth->halt = smsc95xx_halt;
927*4882a593Smuzhiyun 	eth->write_hwaddr = smsc95xx_write_hwaddr;
928*4882a593Smuzhiyun 	eth->priv = ss;
929*4882a593Smuzhiyun 	return 1;
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun #endif /* !CONFIG_DM_ETH */
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun #ifdef CONFIG_DM_ETH
smsc95xx_eth_start(struct udevice * dev)934*4882a593Smuzhiyun static int smsc95xx_eth_start(struct udevice *dev)
935*4882a593Smuzhiyun {
936*4882a593Smuzhiyun 	struct usb_device *udev = dev_get_parent_priv(dev);
937*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
938*4882a593Smuzhiyun 	struct eth_pdata *pdata = dev_get_platdata(dev);
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	/* Driver-model Ethernet ensures we have this */
941*4882a593Smuzhiyun 	priv->have_hwaddr = 1;
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun 
smsc95xx_eth_stop(struct udevice * dev)946*4882a593Smuzhiyun void smsc95xx_eth_stop(struct udevice *dev)
947*4882a593Smuzhiyun {
948*4882a593Smuzhiyun 	debug("** %s()\n", __func__);
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun 
smsc95xx_eth_send(struct udevice * dev,void * packet,int length)951*4882a593Smuzhiyun int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 	return smsc95xx_send_common(&priv->ueth, packet, length);
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun 
smsc95xx_eth_recv(struct udevice * dev,int flags,uchar ** packetp)958*4882a593Smuzhiyun int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
961*4882a593Smuzhiyun 	struct ueth_data *ueth = &priv->ueth;
962*4882a593Smuzhiyun 	uint8_t *ptr;
963*4882a593Smuzhiyun 	int ret, len;
964*4882a593Smuzhiyun 	u32 packet_len;
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	len = usb_ether_get_rx_bytes(ueth, &ptr);
967*4882a593Smuzhiyun 	debug("%s: first try, len=%d\n", __func__, len);
968*4882a593Smuzhiyun 	if (!len) {
969*4882a593Smuzhiyun 		if (!(flags & ETH_RECV_CHECK_DEVICE))
970*4882a593Smuzhiyun 			return -EAGAIN;
971*4882a593Smuzhiyun 		ret = usb_ether_receive(ueth, RX_URB_SIZE);
972*4882a593Smuzhiyun 		if (ret == -EAGAIN)
973*4882a593Smuzhiyun 			return ret;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 		len = usb_ether_get_rx_bytes(ueth, &ptr);
976*4882a593Smuzhiyun 		debug("%s: second try, len=%d\n", __func__, len);
977*4882a593Smuzhiyun 	}
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 	/*
980*4882a593Smuzhiyun 	 * 1st 4 bytes contain the length of the actual data plus error info.
981*4882a593Smuzhiyun 	 * Extract data length.
982*4882a593Smuzhiyun 	 */
983*4882a593Smuzhiyun 	if (len < sizeof(packet_len)) {
984*4882a593Smuzhiyun 		debug("Rx: incomplete packet length\n");
985*4882a593Smuzhiyun 		goto err;
986*4882a593Smuzhiyun 	}
987*4882a593Smuzhiyun 	memcpy(&packet_len, ptr, sizeof(packet_len));
988*4882a593Smuzhiyun 	le32_to_cpus(&packet_len);
989*4882a593Smuzhiyun 	if (packet_len & RX_STS_ES_) {
990*4882a593Smuzhiyun 		debug("Rx: Error header=%#x", packet_len);
991*4882a593Smuzhiyun 		goto err;
992*4882a593Smuzhiyun 	}
993*4882a593Smuzhiyun 	packet_len = ((packet_len & RX_STS_FL_) >> 16);
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	if (packet_len > len - sizeof(packet_len)) {
996*4882a593Smuzhiyun 		debug("Rx: too large packet: %d\n", packet_len);
997*4882a593Smuzhiyun 		goto err;
998*4882a593Smuzhiyun 	}
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun 	*packetp = ptr + sizeof(packet_len);
1001*4882a593Smuzhiyun 	return packet_len - 4;
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun err:
1004*4882a593Smuzhiyun 	usb_ether_advance_rxbuf(ueth, -1);
1005*4882a593Smuzhiyun 	return -EINVAL;
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun 
smsc95xx_free_pkt(struct udevice * dev,uchar * packet,int packet_len)1008*4882a593Smuzhiyun static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun 	packet_len = ALIGN(packet_len + sizeof(u32), 4);
1013*4882a593Smuzhiyun 	usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun 	return 0;
1016*4882a593Smuzhiyun }
1017*4882a593Smuzhiyun 
smsc95xx_write_hwaddr(struct udevice * dev)1018*4882a593Smuzhiyun int smsc95xx_write_hwaddr(struct udevice *dev)
1019*4882a593Smuzhiyun {
1020*4882a593Smuzhiyun 	struct usb_device *udev = dev_get_parent_priv(dev);
1021*4882a593Smuzhiyun 	struct eth_pdata *pdata = dev_get_platdata(dev);
1022*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun 
smsc95xx_read_rom_hwaddr(struct udevice * dev)1027*4882a593Smuzhiyun int smsc95xx_read_rom_hwaddr(struct udevice *dev)
1028*4882a593Smuzhiyun {
1029*4882a593Smuzhiyun 	struct usb_device *udev = dev_get_parent_priv(dev);
1030*4882a593Smuzhiyun 	struct eth_pdata *pdata = dev_get_platdata(dev);
1031*4882a593Smuzhiyun 	int ret;
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 	ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
1034*4882a593Smuzhiyun 	if (ret)
1035*4882a593Smuzhiyun 		memset(pdata->enetaddr, 0, 6);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	return 0;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
smsc95xx_eth_probe(struct udevice * dev)1040*4882a593Smuzhiyun static int smsc95xx_eth_probe(struct udevice *dev)
1041*4882a593Smuzhiyun {
1042*4882a593Smuzhiyun 	struct smsc95xx_private *priv = dev_get_priv(dev);
1043*4882a593Smuzhiyun 	struct ueth_data *ueth = &priv->ueth;
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun 	return usb_ether_register(dev, ueth, RX_URB_SIZE);
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun 
1048*4882a593Smuzhiyun static const struct eth_ops smsc95xx_eth_ops = {
1049*4882a593Smuzhiyun 	.start	= smsc95xx_eth_start,
1050*4882a593Smuzhiyun 	.send	= smsc95xx_eth_send,
1051*4882a593Smuzhiyun 	.recv	= smsc95xx_eth_recv,
1052*4882a593Smuzhiyun 	.free_pkt = smsc95xx_free_pkt,
1053*4882a593Smuzhiyun 	.stop	= smsc95xx_eth_stop,
1054*4882a593Smuzhiyun 	.write_hwaddr = smsc95xx_write_hwaddr,
1055*4882a593Smuzhiyun 	.read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
1056*4882a593Smuzhiyun };
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun U_BOOT_DRIVER(smsc95xx_eth) = {
1059*4882a593Smuzhiyun 	.name	= "smsc95xx_eth",
1060*4882a593Smuzhiyun 	.id	= UCLASS_ETH,
1061*4882a593Smuzhiyun 	.probe = smsc95xx_eth_probe,
1062*4882a593Smuzhiyun 	.ops	= &smsc95xx_eth_ops,
1063*4882a593Smuzhiyun 	.priv_auto_alloc_size = sizeof(struct smsc95xx_private),
1064*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
1065*4882a593Smuzhiyun };
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun static const struct usb_device_id smsc95xx_eth_id_table[] = {
1068*4882a593Smuzhiyun 	{ USB_DEVICE(0x05ac, 0x1402) },
1069*4882a593Smuzhiyun 	{ USB_DEVICE(0x0424, 0xec00) },	/* LAN9512/LAN9514 Ethernet */
1070*4882a593Smuzhiyun 	{ USB_DEVICE(0x0424, 0x9500) },	/* LAN9500 Ethernet */
1071*4882a593Smuzhiyun 	{ USB_DEVICE(0x0424, 0x9730) },	/* LAN9730 Ethernet (HSIC) */
1072*4882a593Smuzhiyun 	{ USB_DEVICE(0x0424, 0x9900) },	/* SMSC9500 USB Ethernet (SAL10) */
1073*4882a593Smuzhiyun 	{ USB_DEVICE(0x0424, 0x9e00) },	/* LAN9500A Ethernet */
1074*4882a593Smuzhiyun 	{ }		/* Terminating entry */
1075*4882a593Smuzhiyun };
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
1078*4882a593Smuzhiyun #endif
1079