1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 Samsung Electronics
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Joonyoung Shim <jy0922.shim@samsung.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/arch/power.h>
13*4882a593Smuzhiyun #include <asm/arch/xhci-exynos.h>
14*4882a593Smuzhiyun
exynos5_usb3_phy_init(struct exynos_usb3_phy * phy)15*4882a593Smuzhiyun void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun u32 reg;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Reset USB 3.0 PHY */
20*4882a593Smuzhiyun writel(0x0, &phy->phy_reg0);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun clrbits_le32(&phy->phy_param0,
23*4882a593Smuzhiyun /* Select PHY CLK source */
24*4882a593Smuzhiyun PHYPARAM0_REF_USE_PAD |
25*4882a593Smuzhiyun /* Set Loss-of-Signal Detector sensitivity */
26*4882a593Smuzhiyun PHYPARAM0_REF_LOSLEVEL_MASK);
27*4882a593Smuzhiyun setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun writel(0x0, &phy->phy_resume);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * Setting the Frame length Adj value[6:1] to default 0x20
34*4882a593Smuzhiyun * See xHCI 1.0 spec, 5.2.4
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun setbits_le32(&phy->link_system,
37*4882a593Smuzhiyun LINKSYSTEM_XHCI_VERSION_CONTROL |
38*4882a593Smuzhiyun LINKSYSTEM_FLADJ(0x20));
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Set Tx De-Emphasis level */
41*4882a593Smuzhiyun clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
42*4882a593Smuzhiyun setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* PHYTEST POWERDOWN Control */
47*4882a593Smuzhiyun clrbits_le32(&phy->phy_test,
48*4882a593Smuzhiyun PHYTEST_POWERDOWN_SSP |
49*4882a593Smuzhiyun PHYTEST_POWERDOWN_HSP);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* UTMI Power Control */
52*4882a593Smuzhiyun writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Use core clock from main PLL */
55*4882a593Smuzhiyun reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
56*4882a593Smuzhiyun /* Default 24Mhz crystal clock */
57*4882a593Smuzhiyun PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
58*4882a593Smuzhiyun PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
59*4882a593Smuzhiyun PHYCLKRST_SSC_REFCLKSEL(0) |
60*4882a593Smuzhiyun /* Force PortReset of PHY */
61*4882a593Smuzhiyun PHYCLKRST_PORTRESET |
62*4882a593Smuzhiyun /* Digital power supply in normal operating mode */
63*4882a593Smuzhiyun PHYCLKRST_RETENABLEN |
64*4882a593Smuzhiyun /* Enable ref clock for SS function */
65*4882a593Smuzhiyun PHYCLKRST_REF_SSP_EN |
66*4882a593Smuzhiyun /* Enable spread spectrum */
67*4882a593Smuzhiyun PHYCLKRST_SSC_EN |
68*4882a593Smuzhiyun /* Power down HS Bias and PLL blocks in suspend mode */
69*4882a593Smuzhiyun PHYCLKRST_COMMONONN;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun writel(reg, &phy->phy_clk_rst);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* giving time to Phy clock to settle before resetting */
74*4882a593Smuzhiyun udelay(10);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun reg &= ~PHYCLKRST_PORTRESET;
77*4882a593Smuzhiyun writel(reg, &phy->phy_clk_rst);
78*4882a593Smuzhiyun }
79