1 /**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
10 * to uboot.
11 *
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
13 *
14 * SPDX-License-Identifier: GPL-2.0
15 */
16 #include <common.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
22 #include <linux/usb/composite.h>
23
24 #include "core.h"
25 #include "gadget.h"
26 #include "io.h"
27
28 #include "linux-compat.h"
29
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
dwc3_ep0_state_string(enum dwc3_ep0_state state)34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
35 {
36 switch (state) {
37 case EP0_UNCONNECTED:
38 return "Unconnected";
39 case EP0_SETUP_PHASE:
40 return "Setup Phase";
41 case EP0_DATA_PHASE:
42 return "Data Phase";
43 case EP0_STATUS_PHASE:
44 return "Status Phase";
45 default:
46 return "UNKNOWN";
47 }
48 }
49
dwc3_ep0_start_trans(struct dwc3 * dwc,u8 epnum,dma_addr_t buf_dma,u32 len,u32 type,unsigned chain)50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
51 u32 len, u32 type, unsigned chain)
52 {
53 struct dwc3_gadget_ep_cmd_params params;
54 struct dwc3_trb *trb;
55 struct dwc3_ep *dep;
56
57 int ret;
58
59 dep = dwc->eps[epnum];
60 if (dep->flags & DWC3_EP_BUSY) {
61 dev_vdbg(dwc->dev, "%s still busy", dep->name);
62 return 0;
63 }
64
65 trb = &dwc->ep0_trb[dep->free_slot];
66
67 if (chain)
68 dep->free_slot++;
69
70 trb->bpl = lower_32_bits(buf_dma);
71 trb->bph = upper_32_bits(buf_dma);
72 trb->size = len;
73 trb->ctrl = type;
74
75 trb->ctrl |= (DWC3_TRB_CTRL_HWO
76 | DWC3_TRB_CTRL_ISP_IMI);
77
78 if (chain)
79 trb->ctrl |= DWC3_TRB_CTRL_CHN;
80 else
81 trb->ctrl |= (DWC3_TRB_CTRL_IOC
82 | DWC3_TRB_CTRL_LST);
83
84 dwc3_flush_cache((uintptr_t)buf_dma, len);
85 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
86
87 if (chain)
88 return 0;
89
90 memset(¶ms, 0, sizeof(params));
91 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
92 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
93
94 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
95 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
96 if (ret < 0) {
97 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
98 return ret;
99 }
100
101 dep->flags |= DWC3_EP_BUSY;
102 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
103 dep->number);
104
105 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
106
107 return 0;
108 }
109
__dwc3_gadget_ep0_queue(struct dwc3_ep * dep,struct dwc3_request * req)110 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
111 struct dwc3_request *req)
112 {
113 struct dwc3 *dwc = dep->dwc;
114
115 req->request.actual = 0;
116 req->request.status = -EINPROGRESS;
117 req->epnum = dep->number;
118
119 list_add_tail(&req->list, &dep->request_list);
120
121 /*
122 * Gadget driver might not be quick enough to queue a request
123 * before we get a Transfer Not Ready event on this endpoint.
124 *
125 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
126 * flag is set, it's telling us that as soon as Gadget queues the
127 * required request, we should kick the transfer here because the
128 * IRQ we were waiting for is long gone.
129 */
130 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
131 unsigned direction;
132
133 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
134
135 if (dwc->ep0state != EP0_DATA_PHASE) {
136 dev_WARN(dwc->dev, "Unexpected pending request\n");
137 return 0;
138 }
139
140 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
141
142 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
143 DWC3_EP0_DIR_IN);
144
145 return 0;
146 }
147
148 /*
149 * In case gadget driver asked us to delay the STATUS phase,
150 * handle it here.
151 */
152 if (dwc->delayed_status) {
153 unsigned direction;
154
155 direction = !dwc->ep0_expect_in;
156 dwc->delayed_status = false;
157 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
158
159 if (dwc->ep0state == EP0_STATUS_PHASE)
160 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
161 else
162 dev_dbg(dwc->dev, "too early for delayed status");
163
164 return 0;
165 }
166
167 /*
168 * Unfortunately we have uncovered a limitation wrt the Data Phase.
169 *
170 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
171 * come before issueing Start Transfer command, but if we do, we will
172 * miss situations where the host starts another SETUP phase instead of
173 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
174 * Layer Compliance Suite.
175 *
176 * The problem surfaces due to the fact that in case of back-to-back
177 * SETUP packets there will be no XferNotReady(DATA) generated and we
178 * will be stuck waiting for XferNotReady(DATA) forever.
179 *
180 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
181 * it tells us to start Data Phase right away. It also mentions that if
182 * we receive a SETUP phase instead of the DATA phase, core will issue
183 * XferComplete for the DATA phase, before actually initiating it in
184 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
185 * can only be used to print some debugging logs, as the core expects
186 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
187 * just so it completes right away, without transferring anything and,
188 * only then, we can go back to the SETUP phase.
189 *
190 * Because of this scenario, SNPS decided to change the programming
191 * model of control transfers and support on-demand transfers only for
192 * the STATUS phase. To fix the issue we have now, we will always wait
193 * for gadget driver to queue the DATA phase's struct usb_request, then
194 * start it right away.
195 *
196 * If we're actually in a 2-stage transfer, we will wait for
197 * XferNotReady(STATUS).
198 */
199 if (dwc->three_stage_setup) {
200 unsigned direction;
201
202 direction = dwc->ep0_expect_in;
203 dwc->ep0state = EP0_DATA_PHASE;
204
205 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
206
207 dep->flags &= ~DWC3_EP0_DIR_IN;
208 }
209
210 return 0;
211 }
212
dwc3_gadget_ep0_queue(struct usb_ep * ep,struct usb_request * request,gfp_t gfp_flags)213 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
214 gfp_t gfp_flags)
215 {
216 struct dwc3_request *req = to_dwc3_request(request);
217 struct dwc3_ep *dep = to_dwc3_ep(ep);
218 struct dwc3 *dwc = dep->dwc;
219
220 unsigned long flags = 0;
221
222 int ret;
223
224 spin_lock_irqsave(&dwc->lock, flags);
225 if (!dep->endpoint.desc) {
226 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
227 request, dep->name);
228 ret = -ESHUTDOWN;
229 goto out;
230 }
231
232 /* we share one TRB for ep0/1 */
233 if (!list_empty(&dep->request_list)) {
234 ret = -EBUSY;
235 goto out;
236 }
237
238 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
239 request, dep->name, request->length,
240 dwc3_ep0_state_string(dwc->ep0state));
241
242 ret = __dwc3_gadget_ep0_queue(dep, req);
243
244 out:
245 spin_unlock_irqrestore(&dwc->lock, flags);
246
247 return ret;
248 }
249
dwc3_ep0_stall_and_restart(struct dwc3 * dwc)250 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
251 {
252 struct dwc3_ep *dep;
253
254 /* reinitialize physical ep1 */
255 dep = dwc->eps[1];
256 dep->flags = DWC3_EP_ENABLED;
257
258 /* stall is always issued on EP0 */
259 dep = dwc->eps[0];
260 __dwc3_gadget_ep_set_halt(dep, 1, false);
261 dep->flags = DWC3_EP_ENABLED;
262 dwc->delayed_status = false;
263
264 if (!list_empty(&dep->request_list)) {
265 struct dwc3_request *req;
266
267 req = next_request(&dep->request_list);
268 dwc3_gadget_giveback(dep, req, -ECONNRESET);
269 }
270
271 dwc->ep0state = EP0_SETUP_PHASE;
272 dwc3_ep0_out_start(dwc);
273 }
274
__dwc3_gadget_ep0_set_halt(struct usb_ep * ep,int value)275 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
276 {
277 struct dwc3_ep *dep = to_dwc3_ep(ep);
278 struct dwc3 *dwc = dep->dwc;
279
280 dwc3_ep0_stall_and_restart(dwc);
281
282 return 0;
283 }
284
dwc3_gadget_ep0_set_halt(struct usb_ep * ep,int value)285 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
286 {
287 unsigned long flags = 0;
288 int ret;
289
290 spin_lock_irqsave(&dwc->lock, flags);
291 ret = __dwc3_gadget_ep0_set_halt(ep, value);
292 spin_unlock_irqrestore(&dwc->lock, flags);
293
294 return ret;
295 }
296
dwc3_ep0_out_start(struct dwc3 * dwc)297 void dwc3_ep0_out_start(struct dwc3 *dwc)
298 {
299 int ret;
300
301 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
302 DWC3_TRBCTL_CONTROL_SETUP, 0);
303 WARN_ON(ret < 0);
304 }
305
dwc3_wIndex_to_dep(struct dwc3 * dwc,__le16 wIndex_le)306 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
307 {
308 struct dwc3_ep *dep;
309 u32 windex = le16_to_cpu(wIndex_le);
310 u32 epnum;
311
312 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
313 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
314 epnum |= 1;
315
316 dep = dwc->eps[epnum];
317 if (dep->flags & DWC3_EP_ENABLED)
318 return dep;
319
320 return NULL;
321 }
322
dwc3_ep0_status_cmpl(struct usb_ep * ep,struct usb_request * req)323 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
324 {
325 }
326 /*
327 * ch 9.4.5
328 */
dwc3_ep0_handle_status(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)329 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
330 struct usb_ctrlrequest *ctrl)
331 {
332 struct dwc3_ep *dep;
333 u32 recip;
334 u32 reg;
335 u16 usb_status = 0;
336 __le16 *response_pkt;
337
338 recip = ctrl->bRequestType & USB_RECIP_MASK;
339 switch (recip) {
340 case USB_RECIP_DEVICE:
341 /*
342 * LTM will be set once we know how to set this in HW.
343 */
344 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
345
346 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
347 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
348 if (reg & DWC3_DCTL_INITU1ENA)
349 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
350 if (reg & DWC3_DCTL_INITU2ENA)
351 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
352 }
353
354 break;
355
356 case USB_RECIP_INTERFACE:
357 /*
358 * Function Remote Wake Capable D0
359 * Function Remote Wakeup D1
360 */
361 break;
362
363 case USB_RECIP_ENDPOINT:
364 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
365 if (!dep)
366 return -EINVAL;
367
368 if (dep->flags & DWC3_EP_STALL)
369 usb_status = 1 << USB_ENDPOINT_HALT;
370 break;
371 default:
372 return -EINVAL;
373 }
374
375 response_pkt = (__le16 *) dwc->setup_buf;
376 *response_pkt = cpu_to_le16(usb_status);
377
378 dep = dwc->eps[0];
379 dwc->ep0_usb_req.dep = dep;
380 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
381 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
382 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
383
384 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
385 }
386
dwc3_ep0_handle_feature(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl,int set)387 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
388 struct usb_ctrlrequest *ctrl, int set)
389 {
390 struct dwc3_ep *dep;
391 u32 recip;
392 u32 wValue;
393 u32 wIndex;
394 u32 reg;
395 int ret;
396 enum usb_device_state state;
397
398 wValue = le16_to_cpu(ctrl->wValue);
399 wIndex = le16_to_cpu(ctrl->wIndex);
400 recip = ctrl->bRequestType & USB_RECIP_MASK;
401 state = dwc->gadget.state;
402
403 switch (recip) {
404 case USB_RECIP_DEVICE:
405
406 switch (wValue) {
407 case USB_DEVICE_REMOTE_WAKEUP:
408 break;
409 /*
410 * 9.4.1 says only only for SS, in AddressState only for
411 * default control pipe
412 */
413 case USB_DEVICE_U1_ENABLE:
414 if (state != USB_STATE_CONFIGURED)
415 return -EINVAL;
416 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
417 return -EINVAL;
418
419 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
420 if (set && !dwc->dis_u1u2_quirk)
421 reg |= DWC3_DCTL_INITU1ENA;
422 else
423 reg &= ~DWC3_DCTL_INITU1ENA;
424 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
425 break;
426
427 case USB_DEVICE_U2_ENABLE:
428 if (state != USB_STATE_CONFIGURED)
429 return -EINVAL;
430 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
431 return -EINVAL;
432
433 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 if (set && !dwc->dis_u1u2_quirk)
435 reg |= DWC3_DCTL_INITU2ENA;
436 else
437 reg &= ~DWC3_DCTL_INITU2ENA;
438 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
439 break;
440
441 case USB_DEVICE_LTM_ENABLE:
442 return -EINVAL;
443
444 case USB_DEVICE_TEST_MODE:
445 if ((wIndex & 0xff) != 0)
446 return -EINVAL;
447 if (!set)
448 return -EINVAL;
449
450 dwc->test_mode_nr = wIndex >> 8;
451 dwc->test_mode = true;
452 break;
453 default:
454 return -EINVAL;
455 }
456 break;
457
458 case USB_RECIP_INTERFACE:
459 switch (wValue) {
460 case USB_INTRF_FUNC_SUSPEND:
461 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
462 /* XXX enable Low power suspend */
463 ;
464 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
465 /* XXX enable remote wakeup */
466 ;
467 break;
468 default:
469 return -EINVAL;
470 }
471 break;
472
473 case USB_RECIP_ENDPOINT:
474 switch (wValue) {
475 case USB_ENDPOINT_HALT:
476 dep = dwc3_wIndex_to_dep(dwc, wIndex);
477 if (!dep)
478 return -EINVAL;
479 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
480 break;
481 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
482 if (ret)
483 return -EINVAL;
484 break;
485 default:
486 return -EINVAL;
487 }
488 break;
489
490 default:
491 return -EINVAL;
492 }
493
494 return 0;
495 }
496
dwc3_ep0_set_address(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)497 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
498 {
499 enum usb_device_state state = dwc->gadget.state;
500 u32 addr;
501 u32 reg;
502
503 addr = le16_to_cpu(ctrl->wValue);
504 if (addr > 127) {
505 dev_dbg(dwc->dev, "invalid device address %d", addr);
506 return -EINVAL;
507 }
508
509 if (state == USB_STATE_CONFIGURED) {
510 dev_dbg(dwc->dev, "trying to set address when configured");
511 return -EINVAL;
512 }
513
514 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
515 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
516 reg |= DWC3_DCFG_DEVADDR(addr);
517 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
518
519 if (addr)
520 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
521 else
522 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
523
524 return 0;
525 }
526
dwc3_ep0_delegate_req(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)527 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
528 {
529 int ret;
530
531 spin_unlock(&dwc->lock);
532 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
533 spin_lock(&dwc->lock);
534 return ret;
535 }
536
dwc3_ep0_set_config(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)537 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
538 {
539 enum usb_device_state state = dwc->gadget.state;
540 u32 cfg;
541 int ret;
542 u32 reg;
543
544 dwc->start_config_issued = false;
545 cfg = le16_to_cpu(ctrl->wValue);
546
547 switch (state) {
548 case USB_STATE_DEFAULT:
549 return -EINVAL;
550
551 case USB_STATE_ADDRESS:
552 ret = dwc3_ep0_delegate_req(dwc, ctrl);
553 /* if the cfg matches and the cfg is non zero */
554 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
555
556 /*
557 * only change state if set_config has already
558 * been processed. If gadget driver returns
559 * USB_GADGET_DELAYED_STATUS, we will wait
560 * to change the state on the next usb_ep_queue()
561 */
562 if (ret == 0)
563 usb_gadget_set_state(&dwc->gadget,
564 USB_STATE_CONFIGURED);
565
566 /*
567 * Enable transition to U1/U2 state when
568 * nothing is pending from application.
569 */
570 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
571 if (dwc->dis_u1u2_quirk)
572 reg &= ~(DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
573 else
574 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
575 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
576
577 dwc->resize_fifos = true;
578 dev_dbg(dwc->dev, "resize FIFOs flag SET");
579 }
580 break;
581
582 case USB_STATE_CONFIGURED:
583 ret = dwc3_ep0_delegate_req(dwc, ctrl);
584 if (!cfg && !ret)
585 usb_gadget_set_state(&dwc->gadget,
586 USB_STATE_ADDRESS);
587 break;
588 default:
589 ret = -EINVAL;
590 }
591 return ret;
592 }
593
dwc3_ep0_set_sel_cmpl(struct usb_ep * ep,struct usb_request * req)594 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
595 {
596 struct dwc3_ep *dep = to_dwc3_ep(ep);
597 struct dwc3 *dwc = dep->dwc;
598
599 u32 param = 0;
600 u32 reg;
601
602 struct timing {
603 u8 u1sel;
604 u8 u1pel;
605 u16 u2sel;
606 u16 u2pel;
607 } __packed timing;
608
609 int ret;
610
611 memcpy(&timing, req->buf, sizeof(timing));
612
613 dwc->u1sel = timing.u1sel;
614 dwc->u1pel = timing.u1pel;
615 dwc->u2sel = le16_to_cpu(timing.u2sel);
616 dwc->u2pel = le16_to_cpu(timing.u2pel);
617
618 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
619 if (reg & DWC3_DCTL_INITU2ENA)
620 param = dwc->u2pel;
621 if (reg & DWC3_DCTL_INITU1ENA)
622 param = dwc->u1pel;
623
624 /*
625 * According to Synopsys Databook, if parameter is
626 * greater than 125, a value of zero should be
627 * programmed in the register.
628 */
629 if (param > 125)
630 param = 0;
631
632 /* now that we have the time, issue DGCMD Set Sel */
633 ret = dwc3_send_gadget_generic_command(dwc,
634 DWC3_DGCMD_SET_PERIODIC_PAR, param);
635 WARN_ON(ret < 0);
636 }
637
dwc3_ep0_set_sel(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)638 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
639 {
640 struct dwc3_ep *dep;
641 enum usb_device_state state = dwc->gadget.state;
642 u16 wLength;
643
644 if (state == USB_STATE_DEFAULT)
645 return -EINVAL;
646
647 wLength = le16_to_cpu(ctrl->wLength);
648
649 if (wLength != 6) {
650 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
651 wLength);
652 return -EINVAL;
653 }
654
655 /*
656 * To handle Set SEL we need to receive 6 bytes from Host. So let's
657 * queue a usb_request for 6 bytes.
658 *
659 * Remember, though, this controller can't handle non-wMaxPacketSize
660 * aligned transfers on the OUT direction, so we queue a request for
661 * wMaxPacketSize instead.
662 */
663 dep = dwc->eps[0];
664 dwc->ep0_usb_req.dep = dep;
665 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
666 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
667 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
668
669 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
670 }
671
dwc3_ep0_set_isoch_delay(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)672 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
673 {
674 u16 wLength;
675 u16 wValue;
676 u16 wIndex;
677
678 wValue = le16_to_cpu(ctrl->wValue);
679 wLength = le16_to_cpu(ctrl->wLength);
680 wIndex = le16_to_cpu(ctrl->wIndex);
681
682 if (wIndex || wLength)
683 return -EINVAL;
684
685 /*
686 * REVISIT It's unclear from Databook what to do with this
687 * value. For now, just cache it.
688 */
689 dwc->isoch_delay = wValue;
690
691 return 0;
692 }
693
dwc3_ep0_std_request(struct dwc3 * dwc,struct usb_ctrlrequest * ctrl)694 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
695 {
696 int ret;
697
698 switch (ctrl->bRequest) {
699 case USB_REQ_GET_STATUS:
700 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
701 ret = dwc3_ep0_handle_status(dwc, ctrl);
702 break;
703 case USB_REQ_CLEAR_FEATURE:
704 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
705 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
706 break;
707 case USB_REQ_SET_FEATURE:
708 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
709 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
710 break;
711 case USB_REQ_SET_ADDRESS:
712 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
713 ret = dwc3_ep0_set_address(dwc, ctrl);
714 break;
715 case USB_REQ_SET_CONFIGURATION:
716 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
717 ret = dwc3_ep0_set_config(dwc, ctrl);
718 break;
719 case USB_REQ_SET_SEL:
720 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
721 ret = dwc3_ep0_set_sel(dwc, ctrl);
722 break;
723 case USB_REQ_SET_ISOCH_DELAY:
724 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
725 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
726 break;
727 default:
728 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
729 ret = dwc3_ep0_delegate_req(dwc, ctrl);
730 break;
731 }
732
733 return ret;
734 }
735
dwc3_ep0_inspect_setup(struct dwc3 * dwc,const struct dwc3_event_depevt * event)736 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
737 const struct dwc3_event_depevt *event)
738 {
739 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
740 int ret = -EINVAL;
741 u32 len;
742
743 if (!dwc->gadget_driver)
744 goto out;
745
746 len = le16_to_cpu(ctrl->wLength);
747 if (!len) {
748 dwc->three_stage_setup = false;
749 dwc->ep0_expect_in = false;
750 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
751 } else {
752 dwc->three_stage_setup = true;
753 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
754 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
755 }
756
757 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
758 ret = dwc3_ep0_std_request(dwc, ctrl);
759 else
760 ret = dwc3_ep0_delegate_req(dwc, ctrl);
761
762 if (ret == USB_GADGET_DELAYED_STATUS)
763 dwc->delayed_status = true;
764
765 out:
766 if (ret < 0)
767 dwc3_ep0_stall_and_restart(dwc);
768 }
769
dwc3_ep0_complete_data(struct dwc3 * dwc,const struct dwc3_event_depevt * event)770 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
771 const struct dwc3_event_depevt *event)
772 {
773 struct dwc3_request *r = NULL;
774 struct usb_request *ur;
775 struct dwc3_trb *trb;
776 struct dwc3_ep *ep0;
777 unsigned transfer_size = 0;
778 unsigned maxp;
779 void *buf;
780 u32 transferred = 0;
781 u32 status;
782 u32 length;
783 u8 epnum;
784
785 epnum = event->endpoint_number;
786 ep0 = dwc->eps[0];
787
788 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
789
790 trb = dwc->ep0_trb;
791
792 r = next_request(&ep0->request_list);
793 if (!r)
794 return;
795
796 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
797
798 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
799 if (status == DWC3_TRBSTS_SETUP_PENDING) {
800 dev_dbg(dwc->dev, "Setup Pending received");
801
802 if (r)
803 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
804
805 return;
806 }
807
808 ur = &r->request;
809 buf = ur->buf;
810
811 length = trb->size & DWC3_TRB_SIZE_MASK;
812
813 maxp = ep0->endpoint.maxpacket;
814
815 if (dwc->ep0_bounced) {
816 /*
817 * Handle the first TRB before handling the bounce buffer if
818 * the request length is greater than the bounce buffer size.
819 */
820 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
821 transfer_size = (ur->length / maxp) * maxp;
822 transferred = transfer_size - length;
823 buf = (u8 *)buf + transferred;
824 ur->actual += transferred;
825
826 trb++;
827 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
828 length = trb->size & DWC3_TRB_SIZE_MASK;
829
830 ep0->free_slot = 0;
831 }
832
833 transfer_size = roundup((ur->length - transfer_size),
834 maxp);
835 transferred = min_t(u32, ur->length - transferred,
836 transfer_size - length);
837 dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
838 memcpy(buf, dwc->ep0_bounce, transferred);
839 } else {
840 transferred = ur->length - length;
841 }
842
843 ur->actual += transferred;
844
845 if ((epnum & 1) && ur->actual < ur->length) {
846 /* for some reason we did not get everything out */
847
848 dwc3_ep0_stall_and_restart(dwc);
849 } else {
850 dwc3_gadget_giveback(ep0, r, 0);
851
852 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
853 ur->length && ur->zero) {
854 int ret;
855
856 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
857
858 ret = dwc3_ep0_start_trans(dwc, epnum,
859 dwc->ctrl_req_addr, 0,
860 DWC3_TRBCTL_CONTROL_DATA, 0);
861 WARN_ON(ret < 0);
862 }
863 }
864 }
865
dwc3_ep0_complete_status(struct dwc3 * dwc,const struct dwc3_event_depevt * event)866 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
867 const struct dwc3_event_depevt *event)
868 {
869 struct dwc3_request *r;
870 struct dwc3_ep *dep;
871 struct dwc3_trb *trb;
872 u32 status;
873
874 dep = dwc->eps[0];
875 trb = dwc->ep0_trb;
876
877 if (!list_empty(&dep->request_list)) {
878 r = next_request(&dep->request_list);
879
880 dwc3_gadget_giveback(dep, r, 0);
881 }
882
883 if (dwc->test_mode) {
884 int ret;
885
886 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
887 if (ret < 0) {
888 dev_dbg(dwc->dev, "Invalid Test #%d",
889 dwc->test_mode_nr);
890 dwc3_ep0_stall_and_restart(dwc);
891 return;
892 }
893 }
894
895 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
896 if (status == DWC3_TRBSTS_SETUP_PENDING)
897 dev_dbg(dwc->dev, "Setup Pending received");
898
899 dwc->ep0state = EP0_SETUP_PHASE;
900 dwc3_ep0_out_start(dwc);
901 }
902
dwc3_ep0_xfer_complete(struct dwc3 * dwc,const struct dwc3_event_depevt * event)903 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
904 const struct dwc3_event_depevt *event)
905 {
906 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
907
908 dep->flags &= ~DWC3_EP_BUSY;
909 dep->resource_index = 0;
910 dwc->setup_packet_pending = false;
911
912 switch (dwc->ep0state) {
913 case EP0_SETUP_PHASE:
914 dev_vdbg(dwc->dev, "Setup Phase");
915 dwc3_ep0_inspect_setup(dwc, event);
916 break;
917
918 case EP0_DATA_PHASE:
919 dev_vdbg(dwc->dev, "Data Phase");
920 dwc3_ep0_complete_data(dwc, event);
921 break;
922
923 case EP0_STATUS_PHASE:
924 dev_vdbg(dwc->dev, "Status Phase");
925 dwc3_ep0_complete_status(dwc, event);
926 break;
927 default:
928 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
929 }
930 }
931
__dwc3_ep0_do_control_data(struct dwc3 * dwc,struct dwc3_ep * dep,struct dwc3_request * req)932 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
933 struct dwc3_ep *dep, struct dwc3_request *req)
934 {
935 int ret;
936
937 req->direction = !!dep->number;
938
939 if (req->request.length == 0) {
940 ret = dwc3_ep0_start_trans(dwc, dep->number,
941 dwc->ctrl_req_addr, 0,
942 DWC3_TRBCTL_CONTROL_DATA, 0);
943 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
944 (dep->number == 0)) {
945 u32 transfer_size = 0;
946 u32 maxpacket;
947
948 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
949 dep->number);
950 if (ret) {
951 dev_dbg(dwc->dev, "failed to map request\n");
952 return;
953 }
954
955 maxpacket = dep->endpoint.maxpacket;
956 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
957 transfer_size = (req->request.length / maxpacket) *
958 maxpacket;
959 ret = dwc3_ep0_start_trans(dwc, dep->number,
960 req->request.dma,
961 transfer_size,
962 DWC3_TRBCTL_CONTROL_DATA, 1);
963 }
964
965 transfer_size = roundup((req->request.length - transfer_size),
966 maxpacket);
967
968 dwc->ep0_bounced = true;
969
970 /*
971 * REVISIT in case request length is bigger than
972 * DWC3_EP0_BOUNCE_SIZE we will need two chained
973 * TRBs to handle the transfer.
974 */
975 ret = dwc3_ep0_start_trans(dwc, dep->number,
976 dwc->ep0_bounce_addr, transfer_size,
977 DWC3_TRBCTL_CONTROL_DATA, 0);
978 } else {
979 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
980 dep->number);
981 if (ret) {
982 dev_dbg(dwc->dev, "failed to map request\n");
983 return;
984 }
985
986 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
987 req->request.length,
988 DWC3_TRBCTL_CONTROL_DATA, 0);
989 }
990
991 WARN_ON(ret < 0);
992 }
993
dwc3_ep0_start_control_status(struct dwc3_ep * dep)994 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
995 {
996 struct dwc3 *dwc = dep->dwc;
997 u32 type;
998
999 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1000 : DWC3_TRBCTL_CONTROL_STATUS2;
1001
1002 return dwc3_ep0_start_trans(dwc, dep->number,
1003 dwc->ctrl_req_addr, 0, type, 0);
1004 }
1005
__dwc3_ep0_do_control_status(struct dwc3 * dwc,struct dwc3_ep * dep)1006 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1007 {
1008 if (dwc->resize_fifos) {
1009 dev_dbg(dwc->dev, "Resizing FIFOs");
1010 dwc3_gadget_resize_tx_fifos(dwc);
1011 dwc->resize_fifos = 0;
1012 }
1013
1014 WARN_ON(dwc3_ep0_start_control_status(dep));
1015 }
1016
dwc3_ep0_do_control_status(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1017 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1018 const struct dwc3_event_depevt *event)
1019 {
1020 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1021
1022 __dwc3_ep0_do_control_status(dwc, dep);
1023 }
1024
dwc3_ep0_end_control_data(struct dwc3 * dwc,struct dwc3_ep * dep)1025 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1026 {
1027 struct dwc3_gadget_ep_cmd_params params;
1028 u32 cmd;
1029 int ret;
1030
1031 if (!dep->resource_index)
1032 return;
1033
1034 cmd = DWC3_DEPCMD_ENDTRANSFER;
1035 cmd |= DWC3_DEPCMD_CMDIOC;
1036 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1037 memset(¶ms, 0, sizeof(params));
1038 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1039 WARN_ON_ONCE(ret);
1040 dep->resource_index = 0;
1041 }
1042
dwc3_ep0_xfernotready(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1043 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1044 const struct dwc3_event_depevt *event)
1045 {
1046 dwc->setup_packet_pending = true;
1047
1048 switch (event->status) {
1049 case DEPEVT_STATUS_CONTROL_DATA:
1050 dev_vdbg(dwc->dev, "Control Data");
1051
1052 /*
1053 * We already have a DATA transfer in the controller's cache,
1054 * if we receive a XferNotReady(DATA) we will ignore it, unless
1055 * it's for the wrong direction.
1056 *
1057 * In that case, we must issue END_TRANSFER command to the Data
1058 * Phase we already have started and issue SetStall on the
1059 * control endpoint.
1060 */
1061 if (dwc->ep0_expect_in != event->endpoint_number) {
1062 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1063
1064 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1065 dwc3_ep0_end_control_data(dwc, dep);
1066 dwc3_ep0_stall_and_restart(dwc);
1067 return;
1068 }
1069
1070 break;
1071
1072 case DEPEVT_STATUS_CONTROL_STATUS:
1073 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1074 return;
1075
1076 dev_vdbg(dwc->dev, "Control Status");
1077
1078 dwc->ep0state = EP0_STATUS_PHASE;
1079
1080 if (dwc->delayed_status) {
1081 WARN_ON_ONCE(event->endpoint_number != 1);
1082 dev_vdbg(dwc->dev, "Delayed Status");
1083 return;
1084 }
1085
1086 dwc3_ep0_do_control_status(dwc, event);
1087 }
1088 }
1089
dwc3_ep0_interrupt(struct dwc3 * dwc,const struct dwc3_event_depevt * event)1090 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1091 const struct dwc3_event_depevt *event)
1092 {
1093 u8 epnum = event->endpoint_number;
1094
1095 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1096 dwc3_ep_event_string(event->endpoint_event),
1097 epnum >> 1, (epnum & 1) ? "in" : "out",
1098 dwc3_ep0_state_string(dwc->ep0state));
1099
1100 switch (event->endpoint_event) {
1101 case DWC3_DEPEVT_XFERCOMPLETE:
1102 dwc3_ep0_xfer_complete(dwc, event);
1103 break;
1104
1105 case DWC3_DEPEVT_XFERNOTREADY:
1106 dwc3_ep0_xfernotready(dwc, event);
1107 break;
1108
1109 case DWC3_DEPEVT_XFERINPROGRESS:
1110 case DWC3_DEPEVT_RXTXFIFOEVT:
1111 case DWC3_DEPEVT_STREAMEVT:
1112 case DWC3_DEPEVT_EPCMDCMPLT:
1113 break;
1114 }
1115 }
1116