xref: /OK3568_Linux_fs/u-boot/drivers/usb/cdns3/drd.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Cadence USB3 DRD header file.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018-2019 Cadence.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Pawel Laszczak <pawell@cadence.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun #ifndef __LINUX_CDNS3_DRD
10*4882a593Smuzhiyun #define __LINUX_CDNS3_DRD
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun #include <linux/usb/otg.h>
14*4882a593Smuzhiyun #include "core.h"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*  DRD register interface for version v1. */
17*4882a593Smuzhiyun struct cdns3_otg_regs {
18*4882a593Smuzhiyun 	__le32 did;
19*4882a593Smuzhiyun 	__le32 rid;
20*4882a593Smuzhiyun 	__le32 capabilities;
21*4882a593Smuzhiyun 	__le32 reserved1;
22*4882a593Smuzhiyun 	__le32 cmd;
23*4882a593Smuzhiyun 	__le32 sts;
24*4882a593Smuzhiyun 	__le32 state;
25*4882a593Smuzhiyun 	__le32 reserved2;
26*4882a593Smuzhiyun 	__le32 ien;
27*4882a593Smuzhiyun 	__le32 ivect;
28*4882a593Smuzhiyun 	__le32 refclk;
29*4882a593Smuzhiyun 	__le32 tmr;
30*4882a593Smuzhiyun 	__le32 reserved3[4];
31*4882a593Smuzhiyun 	__le32 simulate;
32*4882a593Smuzhiyun 	__le32 override;
33*4882a593Smuzhiyun 	__le32 susp_ctrl;
34*4882a593Smuzhiyun 	__le32 reserved4;
35*4882a593Smuzhiyun 	__le32 anasts;
36*4882a593Smuzhiyun 	__le32 adp_ramp_time;
37*4882a593Smuzhiyun 	__le32 ctrl1;
38*4882a593Smuzhiyun 	__le32 ctrl2;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*  DRD register interface for version v0. */
42*4882a593Smuzhiyun struct cdns3_otg_legacy_regs {
43*4882a593Smuzhiyun 	__le32 cmd;
44*4882a593Smuzhiyun 	__le32 sts;
45*4882a593Smuzhiyun 	__le32 state;
46*4882a593Smuzhiyun 	__le32 refclk;
47*4882a593Smuzhiyun 	__le32 ien;
48*4882a593Smuzhiyun 	__le32 ivect;
49*4882a593Smuzhiyun 	__le32 reserved1[3];
50*4882a593Smuzhiyun 	__le32 tmr;
51*4882a593Smuzhiyun 	__le32 reserved2[2];
52*4882a593Smuzhiyun 	__le32 version;
53*4882a593Smuzhiyun 	__le32 capabilities;
54*4882a593Smuzhiyun 	__le32 reserved3[2];
55*4882a593Smuzhiyun 	__le32 simulate;
56*4882a593Smuzhiyun 	__le32 reserved4[5];
57*4882a593Smuzhiyun 	__le32 ctrl1;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * Common registers interface for both version of DRD.
62*4882a593Smuzhiyun  */
63*4882a593Smuzhiyun struct cdns3_otg_common_regs {
64*4882a593Smuzhiyun 	__le32 cmd;
65*4882a593Smuzhiyun 	__le32 sts;
66*4882a593Smuzhiyun 	__le32 state;
67*4882a593Smuzhiyun 	__le32 different1;
68*4882a593Smuzhiyun 	__le32 ien;
69*4882a593Smuzhiyun 	__le32 ivect;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* CDNS_RID - bitmasks */
73*4882a593Smuzhiyun #define CDNS_RID(p)			((p) & GENMASK(15, 0))
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* CDNS_VID - bitmasks */
76*4882a593Smuzhiyun #define CDNS_DID(p)			((p) & GENMASK(31, 0))
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* OTGCMD - bitmasks */
79*4882a593Smuzhiyun /* "Request the bus for Device mode. */
80*4882a593Smuzhiyun #define OTGCMD_DEV_BUS_REQ		BIT(0)
81*4882a593Smuzhiyun /* Request the bus for Host mode */
82*4882a593Smuzhiyun #define OTGCMD_HOST_BUS_REQ		BIT(1)
83*4882a593Smuzhiyun /* Enable OTG mode. */
84*4882a593Smuzhiyun #define OTGCMD_OTG_EN			BIT(2)
85*4882a593Smuzhiyun /* Disable OTG mode */
86*4882a593Smuzhiyun #define OTGCMD_OTG_DIS			BIT(3)
87*4882a593Smuzhiyun /*"Configure OTG as A-Device. */
88*4882a593Smuzhiyun #define OTGCMD_A_DEV_EN			BIT(4)
89*4882a593Smuzhiyun /*"Configure OTG as A-Device. */
90*4882a593Smuzhiyun #define OTGCMD_A_DEV_DIS		BIT(5)
91*4882a593Smuzhiyun /* Drop the bus for Device mod	e. */
92*4882a593Smuzhiyun #define OTGCMD_DEV_BUS_DROP		BIT(8)
93*4882a593Smuzhiyun /* Drop the bus for Host mode*/
94*4882a593Smuzhiyun #define OTGCMD_HOST_BUS_DROP		BIT(9)
95*4882a593Smuzhiyun /* Power Down USBSS-DEV. */
96*4882a593Smuzhiyun #define OTGCMD_DEV_POWER_OFF		BIT(11)
97*4882a593Smuzhiyun /* Power Down CDNSXHCI. */
98*4882a593Smuzhiyun #define OTGCMD_HOST_POWER_OFF		BIT(12)
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* OTGIEN - bitmasks */
101*4882a593Smuzhiyun /* ID change interrupt enable */
102*4882a593Smuzhiyun #define OTGIEN_ID_CHANGE_INT		BIT(0)
103*4882a593Smuzhiyun /* Vbusvalid fall detected interrupt enable.*/
104*4882a593Smuzhiyun #define OTGIEN_VBUSVALID_RISE_INT	BIT(4)
105*4882a593Smuzhiyun /* Vbusvalid fall detected interrupt enable */
106*4882a593Smuzhiyun #define OTGIEN_VBUSVALID_FALL_INT	BIT(5)
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /* OTGSTS - bitmasks */
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun  * Current value of the ID pin. It is only valid when idpullup in
111*4882a593Smuzhiyun  *  OTGCTRL1_TYPE register is set to '1'.
112*4882a593Smuzhiyun  */
113*4882a593Smuzhiyun #define OTGSTS_ID_VALUE			BIT(0)
114*4882a593Smuzhiyun /* Current value of the vbus_valid */
115*4882a593Smuzhiyun #define OTGSTS_VBUS_VALID		BIT(1)
116*4882a593Smuzhiyun /* Current value of the b_sess_vld */
117*4882a593Smuzhiyun #define OTGSTS_SESSION_VALID		BIT(2)
118*4882a593Smuzhiyun /*Device mode is active*/
119*4882a593Smuzhiyun #define OTGSTS_DEV_ACTIVE		BIT(3)
120*4882a593Smuzhiyun /* Host mode is active. */
121*4882a593Smuzhiyun #define OTGSTS_HOST_ACTIVE		BIT(4)
122*4882a593Smuzhiyun /* OTG Controller not ready. */
123*4882a593Smuzhiyun #define OTGSTS_OTG_NRDY_MASK		BIT(11)
124*4882a593Smuzhiyun #define OTGSTS_OTG_NRDY(p)		((p) & OTGSTS_OTG_NRDY_MASK)
125*4882a593Smuzhiyun /*
126*4882a593Smuzhiyun  * Value of the strap pins.
127*4882a593Smuzhiyun  * 000 - no default configuration
128*4882a593Smuzhiyun  * 010 - Controller initiall configured as Host
129*4882a593Smuzhiyun  * 100 - Controller initially configured as Device
130*4882a593Smuzhiyun  */
131*4882a593Smuzhiyun #define OTGSTS_STRAP(p)			(((p) & GENMASK(14, 12)) >> 12)
132*4882a593Smuzhiyun #define OTGSTS_STRAP_NO_DEFAULT_CFG	0x00
133*4882a593Smuzhiyun #define OTGSTS_STRAP_HOST_OTG		0x01
134*4882a593Smuzhiyun #define OTGSTS_STRAP_HOST		0x02
135*4882a593Smuzhiyun #define OTGSTS_STRAP_GADGET		0x04
136*4882a593Smuzhiyun /* Host mode is turned on. */
137*4882a593Smuzhiyun #define OTGSTS_XHCI_READY		BIT(26)
138*4882a593Smuzhiyun /* "Device mode is turned on .*/
139*4882a593Smuzhiyun #define OTGSTS_DEV_READY		BIT(27)
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun /* OTGSTATE- bitmasks */
142*4882a593Smuzhiyun #define OTGSTATE_DEV_STATE_MASK		GENMASK(2, 0)
143*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_MASK	GENMASK(5, 3)
144*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_IDLE	0x0
145*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_VBUS_FALL	0x7
146*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE(p)		(((p) & OTGSTATE_HOST_STATE_MASK) >> 3)
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /* OTGREFCLK - bitmasks */
149*4882a593Smuzhiyun #define OTGREFCLK_STB_CLK_SWITCH_EN	BIT(31)
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /* OVERRIDE - bitmasks */
152*4882a593Smuzhiyun #define OVERRIDE_IDPULLUP		BIT(0)
153*4882a593Smuzhiyun /* Only for CDNS3_CONTROLLER_V0 version */
154*4882a593Smuzhiyun #define OVERRIDE_IDPULLUP_V0		BIT(24)
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun int cdns3_is_host(struct cdns3 *cdns);
157*4882a593Smuzhiyun int cdns3_is_device(struct cdns3 *cdns);
158*4882a593Smuzhiyun int cdns3_get_id(struct cdns3 *cdns);
159*4882a593Smuzhiyun int cdns3_get_vbus(struct cdns3 *cdns);
160*4882a593Smuzhiyun int cdns3_drd_init(struct cdns3 *cdns);
161*4882a593Smuzhiyun int cdns3_drd_exit(struct cdns3 *cdns);
162*4882a593Smuzhiyun int cdns3_drd_update_mode(struct cdns3 *cdns);
163*4882a593Smuzhiyun int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on);
164*4882a593Smuzhiyun int cdns3_drd_switch_host(struct cdns3 *cdns, int on);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #endif /* __LINUX_CDNS3_DRD */
167