1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * TI OMAP timer driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015, Texas Instruments, Incorporated
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <timer.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/arch/clock.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Timer register bits */
19*4882a593Smuzhiyun #define TCLR_START BIT(0) /* Start=1 */
20*4882a593Smuzhiyun #define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
21*4882a593Smuzhiyun #define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */
22*4882a593Smuzhiyun #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct omap_gptimer_regs {
27*4882a593Smuzhiyun unsigned int tidr; /* offset 0x00 */
28*4882a593Smuzhiyun unsigned char res1[12];
29*4882a593Smuzhiyun unsigned int tiocp_cfg; /* offset 0x10 */
30*4882a593Smuzhiyun unsigned char res2[12];
31*4882a593Smuzhiyun unsigned int tier; /* offset 0x20 */
32*4882a593Smuzhiyun unsigned int tistatr; /* offset 0x24 */
33*4882a593Smuzhiyun unsigned int tistat; /* offset 0x28 */
34*4882a593Smuzhiyun unsigned int tisr; /* offset 0x2c */
35*4882a593Smuzhiyun unsigned int tcicr; /* offset 0x30 */
36*4882a593Smuzhiyun unsigned int twer; /* offset 0x34 */
37*4882a593Smuzhiyun unsigned int tclr; /* offset 0x38 */
38*4882a593Smuzhiyun unsigned int tcrr; /* offset 0x3c */
39*4882a593Smuzhiyun unsigned int tldr; /* offset 0x40 */
40*4882a593Smuzhiyun unsigned int ttgr; /* offset 0x44 */
41*4882a593Smuzhiyun unsigned int twpc; /* offset 0x48 */
42*4882a593Smuzhiyun unsigned int tmar; /* offset 0x4c */
43*4882a593Smuzhiyun unsigned int tcar1; /* offset 0x50 */
44*4882a593Smuzhiyun unsigned int tscir; /* offset 0x54 */
45*4882a593Smuzhiyun unsigned int tcar2; /* offset 0x58 */
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Omap Timer Priv */
49*4882a593Smuzhiyun struct omap_timer_priv {
50*4882a593Smuzhiyun struct omap_gptimer_regs *regs;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
omap_timer_get_count(struct udevice * dev,u64 * count)53*4882a593Smuzhiyun static int omap_timer_get_count(struct udevice *dev, u64 *count)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct omap_timer_priv *priv = dev_get_priv(dev);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun *count = readl(&priv->regs->tcrr);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
omap_timer_probe(struct udevice * dev)62*4882a593Smuzhiyun static int omap_timer_probe(struct udevice *dev)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
65*4882a593Smuzhiyun struct omap_timer_priv *priv = dev_get_priv(dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun uc_priv->clock_rate = TIMER_CLOCK;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* start the counter ticking up, reload value on overflow */
70*4882a593Smuzhiyun writel(0, &priv->regs->tldr);
71*4882a593Smuzhiyun /* enable timer */
72*4882a593Smuzhiyun writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
73*4882a593Smuzhiyun TCLR_START, &priv->regs->tclr);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
omap_timer_ofdata_to_platdata(struct udevice * dev)78*4882a593Smuzhiyun static int omap_timer_ofdata_to_platdata(struct udevice *dev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct omap_timer_priv *priv = dev_get_priv(dev);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun priv->regs = map_physmem(devfdt_get_addr(dev),
83*4882a593Smuzhiyun sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct timer_ops omap_timer_ops = {
90*4882a593Smuzhiyun .get_count = omap_timer_get_count,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const struct udevice_id omap_timer_ids[] = {
94*4882a593Smuzhiyun { .compatible = "ti,am335x-timer" },
95*4882a593Smuzhiyun { .compatible = "ti,am4372-timer" },
96*4882a593Smuzhiyun { .compatible = "ti,omap5430-timer" },
97*4882a593Smuzhiyun {}
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun U_BOOT_DRIVER(omap_timer) = {
101*4882a593Smuzhiyun .name = "omap_timer",
102*4882a593Smuzhiyun .id = UCLASS_TIMER,
103*4882a593Smuzhiyun .of_match = omap_timer_ids,
104*4882a593Smuzhiyun .ofdata_to_platdata = omap_timer_ofdata_to_platdata,
105*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct omap_timer_priv),
106*4882a593Smuzhiyun .probe = omap_timer_probe,
107*4882a593Smuzhiyun .ops = &omap_timer_ops,
108*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
109*4882a593Smuzhiyun };
110