1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Microchip Corporation
3*4882a593Smuzhiyun * Wenyou.Yang <wenyou.yang@microchip.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <clk.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <timer.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define AT91_PIT_VALUE 0xfffff
15*4882a593Smuzhiyun #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct atmel_pit_regs {
18*4882a593Smuzhiyun u32 mode;
19*4882a593Smuzhiyun u32 status;
20*4882a593Smuzhiyun u32 value;
21*4882a593Smuzhiyun u32 value_image;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct atmel_pit_platdata {
25*4882a593Smuzhiyun struct atmel_pit_regs *regs;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
atmel_pit_get_count(struct udevice * dev,u64 * count)28*4882a593Smuzhiyun static int atmel_pit_get_count(struct udevice *dev, u64 *count)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct atmel_pit_platdata *plat = dev_get_platdata(dev);
31*4882a593Smuzhiyun struct atmel_pit_regs *const regs = plat->regs;
32*4882a593Smuzhiyun u32 val = readl(®s->value_image);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun *count = timer_conv_64(val);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
atmel_pit_probe(struct udevice * dev)39*4882a593Smuzhiyun static int atmel_pit_probe(struct udevice *dev)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct atmel_pit_platdata *plat = dev_get_platdata(dev);
42*4882a593Smuzhiyun struct atmel_pit_regs *const regs = plat->regs;
43*4882a593Smuzhiyun struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
44*4882a593Smuzhiyun struct clk clk;
45*4882a593Smuzhiyun ulong clk_rate;
46*4882a593Smuzhiyun int ret;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &clk);
49*4882a593Smuzhiyun if (ret)
50*4882a593Smuzhiyun return -EINVAL;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun clk_rate = clk_get_rate(&clk);
53*4882a593Smuzhiyun if (!clk_rate)
54*4882a593Smuzhiyun return -EINVAL;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun uc_priv->clock_rate = clk_rate / 16;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
atmel_pit_ofdata_to_platdata(struct udevice * dev)63*4882a593Smuzhiyun static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct atmel_pit_platdata *plat = dev_get_platdata(dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct timer_ops atmel_pit_ops = {
73*4882a593Smuzhiyun .get_count = atmel_pit_get_count,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct udevice_id atmel_pit_ids[] = {
77*4882a593Smuzhiyun { .compatible = "atmel,at91sam9260-pit" },
78*4882a593Smuzhiyun { }
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun U_BOOT_DRIVER(atmel_pit) = {
82*4882a593Smuzhiyun .name = "atmel_pit",
83*4882a593Smuzhiyun .id = UCLASS_TIMER,
84*4882a593Smuzhiyun .of_match = atmel_pit_ids,
85*4882a593Smuzhiyun .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
86*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
87*4882a593Smuzhiyun .probe = atmel_pit_probe,
88*4882a593Smuzhiyun .ops = &atmel_pit_ops,
89*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
90*4882a593Smuzhiyun };
91