1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Synopsys, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <timer.h>
11*4882a593Smuzhiyun #include <asm/arcregs.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define NH_MODE (1 << 1)
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * ARC timer control registers are mapped to auxiliary address space.
20*4882a593Smuzhiyun * There are special ARC asm command to access that addresses.
21*4882a593Smuzhiyun * Therefore we use built-in functions to read from and write to timer
22*4882a593Smuzhiyun * control register.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Driver private data. Contains timer id. Could be either 0 or 1. */
26*4882a593Smuzhiyun struct arc_timer_priv {
27*4882a593Smuzhiyun uint timer_id;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
arc_timer_get_count(struct udevice * dev,u64 * count)30*4882a593Smuzhiyun static int arc_timer_get_count(struct udevice *dev, u64 *count)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun u32 val = 0;
33*4882a593Smuzhiyun struct arc_timer_priv *priv = dev_get_priv(dev);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun switch (priv->timer_id) {
36*4882a593Smuzhiyun case 0:
37*4882a593Smuzhiyun val = read_aux_reg(ARC_AUX_TIMER0_CNT);
38*4882a593Smuzhiyun break;
39*4882a593Smuzhiyun case 1:
40*4882a593Smuzhiyun val = read_aux_reg(ARC_AUX_TIMER1_CNT);
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun *count = timer_conv_64(val);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
arc_timer_probe(struct udevice * dev)48*4882a593Smuzhiyun static int arc_timer_probe(struct udevice *dev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int id;
51*4882a593Smuzhiyun struct arc_timer_priv *priv = dev_get_priv(dev);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Get registers offset and size */
54*4882a593Smuzhiyun id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
55*4882a593Smuzhiyun if (id < 0)
56*4882a593Smuzhiyun return -EINVAL;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (id > 1)
59*4882a593Smuzhiyun return -ENXIO;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun priv->timer_id = (uint)id;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * In ARC core there're special registers (Auxiliary or AUX) in its
65*4882a593Smuzhiyun * separate memory space that are used for accessing some hardware
66*4882a593Smuzhiyun * features of the core. They are not mapped in normal memory space
67*4882a593Smuzhiyun * and also always have the same location regardless core configuration.
68*4882a593Smuzhiyun * Thus to simplify understanding of the programming model we chose to
69*4882a593Smuzhiyun * access AUX regs of Timer0 and Timer1 separately instead of using
70*4882a593Smuzhiyun * offsets from some base address.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun switch (priv->timer_id) {
74*4882a593Smuzhiyun case 0:
75*4882a593Smuzhiyun /* Disable timer if CPU is halted */
76*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
77*4882a593Smuzhiyun /* Set max value for counter/timer */
78*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
79*4882a593Smuzhiyun /* Set initial count value and restart counter/timer */
80*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
81*4882a593Smuzhiyun break;
82*4882a593Smuzhiyun case 1:
83*4882a593Smuzhiyun /* Disable timer if CPU is halted */
84*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER1_CTRL, NH_MODE);
85*4882a593Smuzhiyun /* Set max value for counter/timer */
86*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER1_LIMIT, 0xffffffff);
87*4882a593Smuzhiyun /* Set initial count value and restart counter/timer */
88*4882a593Smuzhiyun write_aux_reg(ARC_AUX_TIMER1_CNT, 0);
89*4882a593Smuzhiyun break;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct timer_ops arc_timer_ops = {
97*4882a593Smuzhiyun .get_count = arc_timer_get_count,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct udevice_id arc_timer_ids[] = {
101*4882a593Smuzhiyun { .compatible = "snps,arc-timer" },
102*4882a593Smuzhiyun {}
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun U_BOOT_DRIVER(arc_timer) = {
106*4882a593Smuzhiyun .name = "arc_timer",
107*4882a593Smuzhiyun .id = UCLASS_TIMER,
108*4882a593Smuzhiyun .of_match = arc_timer_ids,
109*4882a593Smuzhiyun .probe = arc_timer_probe,
110*4882a593Smuzhiyun .ops = &arc_timer_ops,
111*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
112*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct arc_timer_priv),
113*4882a593Smuzhiyun };
114