1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2002
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
6*4882a593Smuzhiyun * Scott McNutt <smcnutt@psyent.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <dm.h>
13*4882a593Smuzhiyun #include <errno.h>
14*4882a593Smuzhiyun #include <timer.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* control register */
20*4882a593Smuzhiyun #define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
21*4882a593Smuzhiyun #define ALTERA_TIMER_START BIT(2) /* Start timer */
22*4882a593Smuzhiyun #define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct altera_timer_regs {
25*4882a593Smuzhiyun u32 status; /* Timer status reg */
26*4882a593Smuzhiyun u32 control; /* Timer control reg */
27*4882a593Smuzhiyun u32 periodl; /* Timeout period low */
28*4882a593Smuzhiyun u32 periodh; /* Timeout period high */
29*4882a593Smuzhiyun u32 snapl; /* Snapshot low */
30*4882a593Smuzhiyun u32 snaph; /* Snapshot high */
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct altera_timer_platdata {
34*4882a593Smuzhiyun struct altera_timer_regs *regs;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
altera_timer_get_count(struct udevice * dev,u64 * count)37*4882a593Smuzhiyun static int altera_timer_get_count(struct udevice *dev, u64 *count)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct altera_timer_platdata *plat = dev->platdata;
40*4882a593Smuzhiyun struct altera_timer_regs *const regs = plat->regs;
41*4882a593Smuzhiyun u32 val;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Trigger update */
44*4882a593Smuzhiyun writel(0x0, ®s->snapl);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Read timer value */
47*4882a593Smuzhiyun val = readl(®s->snapl) & 0xffff;
48*4882a593Smuzhiyun val |= (readl(®s->snaph) & 0xffff) << 16;
49*4882a593Smuzhiyun *count = timer_conv_64(~val);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
altera_timer_probe(struct udevice * dev)54*4882a593Smuzhiyun static int altera_timer_probe(struct udevice *dev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct altera_timer_platdata *plat = dev->platdata;
57*4882a593Smuzhiyun struct altera_timer_regs *const regs = plat->regs;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun writel(0, ®s->status);
60*4882a593Smuzhiyun writel(0, ®s->control);
61*4882a593Smuzhiyun writel(ALTERA_TIMER_STOP, ®s->control);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun writel(0xffff, ®s->periodl);
64*4882a593Smuzhiyun writel(0xffff, ®s->periodh);
65*4882a593Smuzhiyun writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
altera_timer_ofdata_to_platdata(struct udevice * dev)70*4882a593Smuzhiyun static int altera_timer_ofdata_to_platdata(struct udevice *dev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct altera_timer_platdata *plat = dev_get_platdata(dev);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun plat->regs = map_physmem(devfdt_get_addr(dev),
75*4882a593Smuzhiyun sizeof(struct altera_timer_regs),
76*4882a593Smuzhiyun MAP_NOCACHE);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct timer_ops altera_timer_ops = {
82*4882a593Smuzhiyun .get_count = altera_timer_get_count,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct udevice_id altera_timer_ids[] = {
86*4882a593Smuzhiyun { .compatible = "altr,timer-1.0" },
87*4882a593Smuzhiyun {}
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun U_BOOT_DRIVER(altera_timer) = {
91*4882a593Smuzhiyun .name = "altera_timer",
92*4882a593Smuzhiyun .id = UCLASS_TIMER,
93*4882a593Smuzhiyun .of_match = altera_timer_ids,
94*4882a593Smuzhiyun .ofdata_to_platdata = altera_timer_ofdata_to_platdata,
95*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
96*4882a593Smuzhiyun .probe = altera_timer_probe,
97*4882a593Smuzhiyun .ops = &altera_timer_ops,
98*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
99*4882a593Smuzhiyun };
100