1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Andestech ATFTMR010 timer driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2016
5*4882a593Smuzhiyun * Rick Chen, NDS32 Software Engineering, rick@andestech.com
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <timer.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Timer Control Register
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun #define T3_UPDOWN (1 << 11)
21*4882a593Smuzhiyun #define T2_UPDOWN (1 << 10)
22*4882a593Smuzhiyun #define T1_UPDOWN (1 << 9)
23*4882a593Smuzhiyun #define T3_OFENABLE (1 << 8)
24*4882a593Smuzhiyun #define T3_CLOCK (1 << 7)
25*4882a593Smuzhiyun #define T3_ENABLE (1 << 6)
26*4882a593Smuzhiyun #define T2_OFENABLE (1 << 5)
27*4882a593Smuzhiyun #define T2_CLOCK (1 << 4)
28*4882a593Smuzhiyun #define T2_ENABLE (1 << 3)
29*4882a593Smuzhiyun #define T1_OFENABLE (1 << 2)
30*4882a593Smuzhiyun #define T1_CLOCK (1 << 1)
31*4882a593Smuzhiyun #define T1_ENABLE (1 << 0)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Timer Interrupt State & Mask Registers
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define T3_OVERFLOW (1 << 8)
37*4882a593Smuzhiyun #define T3_MATCH2 (1 << 7)
38*4882a593Smuzhiyun #define T3_MATCH1 (1 << 6)
39*4882a593Smuzhiyun #define T2_OVERFLOW (1 << 5)
40*4882a593Smuzhiyun #define T2_MATCH2 (1 << 4)
41*4882a593Smuzhiyun #define T2_MATCH1 (1 << 3)
42*4882a593Smuzhiyun #define T1_OVERFLOW (1 << 2)
43*4882a593Smuzhiyun #define T1_MATCH2 (1 << 1)
44*4882a593Smuzhiyun #define T1_MATCH1 (1 << 0)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct atftmr_timer_regs {
47*4882a593Smuzhiyun u32 t1_counter; /* 0x00 */
48*4882a593Smuzhiyun u32 t1_load; /* 0x04 */
49*4882a593Smuzhiyun u32 t1_match1; /* 0x08 */
50*4882a593Smuzhiyun u32 t1_match2; /* 0x0c */
51*4882a593Smuzhiyun u32 t2_counter; /* 0x10 */
52*4882a593Smuzhiyun u32 t2_load; /* 0x14 */
53*4882a593Smuzhiyun u32 t2_match1; /* 0x18 */
54*4882a593Smuzhiyun u32 t2_match2; /* 0x1c */
55*4882a593Smuzhiyun u32 t3_counter; /* 0x20 */
56*4882a593Smuzhiyun u32 t3_load; /* 0x24 */
57*4882a593Smuzhiyun u32 t3_match1; /* 0x28 */
58*4882a593Smuzhiyun u32 t3_match2; /* 0x2c */
59*4882a593Smuzhiyun u32 cr; /* 0x30 */
60*4882a593Smuzhiyun u32 int_state; /* 0x34 */
61*4882a593Smuzhiyun u32 int_mask; /* 0x38 */
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct atftmr_timer_platdata {
65*4882a593Smuzhiyun struct atftmr_timer_regs *regs;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
atftmr_timer_get_count(struct udevice * dev,u64 * count)68*4882a593Smuzhiyun static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev->platdata;
71*4882a593Smuzhiyun struct atftmr_timer_regs *const regs = plat->regs;
72*4882a593Smuzhiyun u32 val;
73*4882a593Smuzhiyun val = readl(®s->t3_counter);
74*4882a593Smuzhiyun *count = timer_conv_64(val);
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
atftmr_timer_probe(struct udevice * dev)78*4882a593Smuzhiyun static int atftmr_timer_probe(struct udevice *dev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev->platdata;
81*4882a593Smuzhiyun struct atftmr_timer_regs *const regs = plat->regs;
82*4882a593Smuzhiyun u32 cr;
83*4882a593Smuzhiyun writel(0, ®s->t3_load);
84*4882a593Smuzhiyun writel(0, ®s->t3_counter);
85*4882a593Smuzhiyun writel(TIMER_LOAD_VAL, ®s->t3_match1);
86*4882a593Smuzhiyun writel(TIMER_LOAD_VAL, ®s->t3_match2);
87*4882a593Smuzhiyun /* disable interrupts */
88*4882a593Smuzhiyun writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask);
89*4882a593Smuzhiyun cr = readl(®s->cr);
90*4882a593Smuzhiyun cr |= (T3_ENABLE|T3_UPDOWN);
91*4882a593Smuzhiyun writel(cr, ®s->cr);
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
atftme_timer_ofdata_to_platdata(struct udevice * dev)95*4882a593Smuzhiyun static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
98*4882a593Smuzhiyun plat->regs = map_physmem(devfdt_get_addr(dev),
99*4882a593Smuzhiyun sizeof(struct atftmr_timer_regs),
100*4882a593Smuzhiyun MAP_NOCACHE);
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct timer_ops ag101p_timer_ops = {
105*4882a593Smuzhiyun .get_count = atftmr_timer_get_count,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct udevice_id ag101p_timer_ids[] = {
109*4882a593Smuzhiyun { .compatible = "andestech,attmr010" },
110*4882a593Smuzhiyun {}
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun U_BOOT_DRIVER(altera_timer) = {
114*4882a593Smuzhiyun .name = "ag101p_timer",
115*4882a593Smuzhiyun .id = UCLASS_TIMER,
116*4882a593Smuzhiyun .of_match = ag101p_timer_ids,
117*4882a593Smuzhiyun .ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
118*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
119*4882a593Smuzhiyun .probe = atftmr_timer_probe,
120*4882a593Smuzhiyun .ops = &ag101p_timer_ops,
121*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
122*4882a593Smuzhiyun };
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