1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Andestech ATCPIT100 timer driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2016
5*4882a593Smuzhiyun * Rick Chen, NDS32 Software Engineering, rick@andestech.com
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <timer.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Definition of register offsets
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* ID and Revision Register */
24*4882a593Smuzhiyun #define ID_REV 0x0
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Configuration Register */
27*4882a593Smuzhiyun #define CFG 0x10
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Interrupt Enable Register */
30*4882a593Smuzhiyun #define INT_EN 0x14
31*4882a593Smuzhiyun #define CH_INT_EN(c , i) ((1<<i)<<(4*c))
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Interrupt Status Register */
34*4882a593Smuzhiyun #define INT_STA 0x18
35*4882a593Smuzhiyun #define CH_INT_STA(c , i) ((1<<i)<<(4*c))
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Channel Enable Register */
38*4882a593Smuzhiyun #define CH_EN 0x1C
39*4882a593Smuzhiyun #define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Ch n Control REgister */
42*4882a593Smuzhiyun #define CH_CTL(n) (0x20+0x10*n)
43*4882a593Smuzhiyun /* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
44*4882a593Smuzhiyun #define APB_CLK (1<<3)
45*4882a593Smuzhiyun /* Channel mode , bit 0~2 */
46*4882a593Smuzhiyun #define TMR_32 1
47*4882a593Smuzhiyun #define TMR_16 2
48*4882a593Smuzhiyun #define TMR_8 3
49*4882a593Smuzhiyun #define PWM 4
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define CH_REL(n) (0x24+0x10*n)
52*4882a593Smuzhiyun #define CH_CNT(n) (0x28+0x10*n)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct atctmr_timer_regs {
55*4882a593Smuzhiyun u32 id_rev; /* 0x00 */
56*4882a593Smuzhiyun u32 reservd[3]; /* 0x04 ~ 0x0c */
57*4882a593Smuzhiyun u32 cfg; /* 0x10 */
58*4882a593Smuzhiyun u32 int_en; /* 0x14 */
59*4882a593Smuzhiyun u32 int_st; /* 0x18 */
60*4882a593Smuzhiyun u32 ch_en; /* 0x1c */
61*4882a593Smuzhiyun u32 ch0_ctrl; /* 0x20 */
62*4882a593Smuzhiyun u32 ch0_reload; /* 0x24 */
63*4882a593Smuzhiyun u32 ch0_cntr; /* 0x28 */
64*4882a593Smuzhiyun u32 reservd1; /* 0x2c */
65*4882a593Smuzhiyun u32 ch1_ctrl; /* 0x30 */
66*4882a593Smuzhiyun u32 ch1_reload; /* 0x34 */
67*4882a593Smuzhiyun u32 int_mask; /* 0x38 */
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct atftmr_timer_platdata {
71*4882a593Smuzhiyun unsigned long *regs;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
atftmr_timer_get_count(struct udevice * dev,u64 * count)74*4882a593Smuzhiyun static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev->platdata;
77*4882a593Smuzhiyun u32 val;
78*4882a593Smuzhiyun val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
79*4882a593Smuzhiyun *count = timer_conv_64(val);
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
atctmr_timer_probe(struct udevice * dev)83*4882a593Smuzhiyun static int atctmr_timer_probe(struct udevice *dev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev->platdata;
86*4882a593Smuzhiyun REG32_TMR(CH_REL(1)) = 0xffffffff;
87*4882a593Smuzhiyun REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
88*4882a593Smuzhiyun REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
atctme_timer_ofdata_to_platdata(struct udevice * dev)92*4882a593Smuzhiyun static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
95*4882a593Smuzhiyun plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct timer_ops ag101p_timer_ops = {
100*4882a593Smuzhiyun .get_count = atftmr_timer_get_count,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct udevice_id ag101p_timer_ids[] = {
104*4882a593Smuzhiyun { .compatible = "andestech,atcpit100" },
105*4882a593Smuzhiyun {}
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun U_BOOT_DRIVER(altera_timer) = {
109*4882a593Smuzhiyun .name = "ae3xx_timer",
110*4882a593Smuzhiyun .id = UCLASS_TIMER,
111*4882a593Smuzhiyun .of_match = ag101p_timer_ids,
112*4882a593Smuzhiyun .ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
113*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
114*4882a593Smuzhiyun .probe = atctmr_timer_probe,
115*4882a593Smuzhiyun .ops = &ag101p_timer_ops,
116*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
117*4882a593Smuzhiyun };
118