xref: /OK3568_Linux_fs/u-boot/drivers/sysreset/sysreset_xtfpga.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Cadence Tensilica xtfpga system reset driver.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * (C) Copyright 2016 Cadence Design Systems Inc.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <errno.h>
12*4882a593Smuzhiyun #include <sysreset.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun 
xtfpga_reset_request(struct udevice * dev,enum sysreset_t type)15*4882a593Smuzhiyun static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	switch (type) {
18*4882a593Smuzhiyun 	case SYSRESET_COLD:
19*4882a593Smuzhiyun 		writel(CONFIG_SYS_FPGAREG_RESET_CODE,
20*4882a593Smuzhiyun 		       CONFIG_SYS_FPGAREG_RESET);
21*4882a593Smuzhiyun 		break;
22*4882a593Smuzhiyun 	default:
23*4882a593Smuzhiyun 		return -EPROTONOSUPPORT;
24*4882a593Smuzhiyun 	}
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	return -EINPROGRESS;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static struct sysreset_ops xtfpga_sysreset_ops = {
30*4882a593Smuzhiyun 	.request	= xtfpga_reset_request,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun U_BOOT_DRIVER(xtfpga_sysreset) = {
34*4882a593Smuzhiyun 	.name	= "xtfpga_sysreset",
35*4882a593Smuzhiyun 	.id	= UCLASS_SYSRESET,
36*4882a593Smuzhiyun 	.ops	= &xtfpga_sysreset_ops,
37*4882a593Smuzhiyun };
38