1 /*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <sysreset.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <linux/err.h>
14
rockchip_sysreset_request(struct udevice * dev,enum sysreset_t type)15 int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
16 {
17 struct sysreset_reg *offset = dev_get_priv(dev);
18 unsigned long cru_base = (unsigned long)dev_read_addr_ptr(dev->parent);
19
20 if (IS_ERR_VALUE(cru_base))
21 return (int)cru_base;
22
23 switch (type) {
24 case SYSRESET_WARM:
25 #ifdef CONFIG_ARM64
26 /* Rockchip 64bit SOC need fst reset for cpu reset entry */
27 writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
28 #else
29 writel(0xeca8, cru_base + offset->glb_srst_snd_value);
30 #endif
31 break;
32 case SYSRESET_COLD:
33 writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
34 break;
35 default:
36 return -EPROTONOSUPPORT;
37 }
38
39 return -EINPROGRESS;
40 }
41
42 static struct sysreset_ops rockchip_sysreset = {
43 .request = rockchip_sysreset_request,
44 };
45
46 U_BOOT_DRIVER(sysreset_rockchip) = {
47 .name = "rockchip_sysreset",
48 .id = UCLASS_SYSRESET,
49 .ops = &rockchip_sysreset,
50 };
51