xref: /OK3568_Linux_fs/u-boot/drivers/sysreset/sysreset_rockchip.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <sysreset.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/clock.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun 
rockchip_sysreset_request(struct udevice * dev,enum sysreset_t type)15*4882a593Smuzhiyun int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	struct sysreset_reg *offset = dev_get_priv(dev);
18*4882a593Smuzhiyun 	unsigned long cru_base = (unsigned long)dev_read_addr_ptr(dev->parent);
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	if (IS_ERR_VALUE(cru_base))
21*4882a593Smuzhiyun 		return (int)cru_base;
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	switch (type) {
24*4882a593Smuzhiyun 	case SYSRESET_WARM:
25*4882a593Smuzhiyun #ifdef CONFIG_ARM64
26*4882a593Smuzhiyun 		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
27*4882a593Smuzhiyun 		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
28*4882a593Smuzhiyun #else
29*4882a593Smuzhiyun 		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun 		break;
32*4882a593Smuzhiyun 	case SYSRESET_COLD:
33*4882a593Smuzhiyun 		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
34*4882a593Smuzhiyun 		break;
35*4882a593Smuzhiyun 	default:
36*4882a593Smuzhiyun 		return -EPROTONOSUPPORT;
37*4882a593Smuzhiyun 	}
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	return -EINPROGRESS;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun static struct sysreset_ops rockchip_sysreset = {
43*4882a593Smuzhiyun 	.request	= rockchip_sysreset_request,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun U_BOOT_DRIVER(sysreset_rockchip) = {
47*4882a593Smuzhiyun 	.name	= "rockchip_sysreset",
48*4882a593Smuzhiyun 	.id	= UCLASS_SYSRESET,
49*4882a593Smuzhiyun 	.ops	= &rockchip_sysreset,
50*4882a593Smuzhiyun };
51