1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# (C) Copyright 2016 Cadence Design Systems Inc. 3*4882a593Smuzhiyun# 4*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyunobj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunifndef CONFIG_SUPPORT_USBPLUG 10*4882a593Smuzhiyunobj-$(CONFIG_$(SPL_TPL_)SYSRESET_SYSCON_REBOOT) += sysreset-syscon-reboot.o 11*4882a593Smuzhiyunobj-$(CONFIG_$(SPL_TPL_)SYSRESET_PSCI) += sysreset_psci.o 12*4882a593Smuzhiyunendif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunobj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o 15*4882a593Smuzhiyunobj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunobj-$(CONFIG_SANDBOX) += sysreset_sandbox.o 18*4882a593Smuzhiyunobj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o 19*4882a593Smuzhiyunobj-$(CONFIG_ARCH_STI) += sysreset_sti.o 20*4882a593Smuzhiyunobj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o 21*4882a593Smuzhiyunobj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunifndef CONFIG_TPL_BUILD 24*4882a593Smuzhiyunobj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o 25*4882a593Smuzhiyunendif 26