1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * SPI driver for rockchip 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Google, Inc 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2008-2013 Rockchip Electronics 7*4882a593Smuzhiyun * Peter, Software Engineering, <superpeter.cai@gmail.com>. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __RK_SPI_H 13*4882a593Smuzhiyun #define __RK_SPI_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct rockchip_spi { 16*4882a593Smuzhiyun u32 ctrlr0; 17*4882a593Smuzhiyun u32 ctrlr1; 18*4882a593Smuzhiyun u32 enr; 19*4882a593Smuzhiyun u32 ser; 20*4882a593Smuzhiyun u32 baudr; 21*4882a593Smuzhiyun u32 txftlr; 22*4882a593Smuzhiyun u32 rxftlr; 23*4882a593Smuzhiyun u32 txflr; 24*4882a593Smuzhiyun u32 rxflr; 25*4882a593Smuzhiyun u32 sr; 26*4882a593Smuzhiyun u32 ipr; 27*4882a593Smuzhiyun u32 imr; 28*4882a593Smuzhiyun u32 isr; 29*4882a593Smuzhiyun u32 risr; 30*4882a593Smuzhiyun u32 icr; 31*4882a593Smuzhiyun u32 dmacr; 32*4882a593Smuzhiyun u32 dmatdlr; 33*4882a593Smuzhiyun u32 dmardlr; /* 0x44 */ 34*4882a593Smuzhiyun u32 reserved[0xef]; 35*4882a593Smuzhiyun u32 txdr[0x100]; /* 0x400 */ 36*4882a593Smuzhiyun u32 rxdr[0x100]; /* 0x800 */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* CTRLR0 */ 40*4882a593Smuzhiyun enum { 41*4882a593Smuzhiyun DFS_SHIFT = 0, /* Data Frame Size */ 42*4882a593Smuzhiyun DFS_MASK = 3, 43*4882a593Smuzhiyun DFS_4BIT = 0, 44*4882a593Smuzhiyun DFS_8BIT, 45*4882a593Smuzhiyun DFS_16BIT, 46*4882a593Smuzhiyun DFS_RESV, 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun CFS_SHIFT = 2, /* Control Frame Size */ 49*4882a593Smuzhiyun CFS_MASK = 0xf, 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun SCPH_SHIFT = 6, /* Serial Clock Phase */ 52*4882a593Smuzhiyun SCPH_MASK = 1, 53*4882a593Smuzhiyun SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */ 54*4882a593Smuzhiyun SCPH_TOGSTA, /* SCLK toggles at start of first data bit */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun SCOL_SHIFT = 7, /* Serial Clock Polarity */ 57*4882a593Smuzhiyun SCOL_MASK = 1, 58*4882a593Smuzhiyun SCOL_LOW = 0, /* Inactive state of serial clock is low */ 59*4882a593Smuzhiyun SCOL_HIGH, /* Inactive state of serial clock is high */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun CSM_SHIFT = 8, /* Chip Select Mode */ 62*4882a593Smuzhiyun CSM_MASK = 0x3, 63*4882a593Smuzhiyun CSM_KEEP = 0, /* ss_n stays low after each frame */ 64*4882a593Smuzhiyun CSM_HALF, /* ss_n high for half sclk_out cycles */ 65*4882a593Smuzhiyun CSM_ONE, /* ss_n high for one sclk_out cycle */ 66*4882a593Smuzhiyun CSM_RESV, 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */ 69*4882a593Smuzhiyun SSN_DELAY_MASK = 1, 70*4882a593Smuzhiyun SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */ 71*4882a593Smuzhiyun SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun SEM_SHIFT = 11, /* Serial Endian Mode */ 74*4882a593Smuzhiyun SEM_MASK = 1, 75*4882a593Smuzhiyun SEM_LITTLE = 0, /* little endian */ 76*4882a593Smuzhiyun SEM_BIG, /* big endian */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun FBM_SHIFT = 12, /* First Bit Mode */ 79*4882a593Smuzhiyun FBM_MASK = 1, 80*4882a593Smuzhiyun FBM_MSB = 0, /* first bit is MSB */ 81*4882a593Smuzhiyun FBM_LSB, /* first bit in LSB */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */ 84*4882a593Smuzhiyun HALF_WORD_MASK = 1, 85*4882a593Smuzhiyun HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */ 86*4882a593Smuzhiyun HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */ 89*4882a593Smuzhiyun RXDSD_MASK = 3, 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun FRF_SHIFT = 16, /* Frame Format */ 92*4882a593Smuzhiyun FRF_MASK = 3, 93*4882a593Smuzhiyun FRF_SPI = 0, /* Motorola SPI */ 94*4882a593Smuzhiyun FRF_SSP, /* Texas Instruments SSP*/ 95*4882a593Smuzhiyun FRF_MICROWIRE, /* National Semiconductors Microwire */ 96*4882a593Smuzhiyun FRF_RESV, 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun TMOD_SHIFT = 18, /* Transfer Mode */ 99*4882a593Smuzhiyun TMOD_MASK = 3, 100*4882a593Smuzhiyun TMOD_TR = 0, /* xmit & recv */ 101*4882a593Smuzhiyun TMOD_TO, /* xmit only */ 102*4882a593Smuzhiyun TMOD_RO, /* recv only */ 103*4882a593Smuzhiyun TMOD_RESV, 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun OMOD_SHIFT = 20, /* Operation Mode */ 106*4882a593Smuzhiyun OMOD_MASK = 1, 107*4882a593Smuzhiyun OMOD_MASTER = 0, /* Master Mode */ 108*4882a593Smuzhiyun OMOD_SLAVE, /* Slave Mode */ 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* SR */ 112*4882a593Smuzhiyun enum { 113*4882a593Smuzhiyun SR_MASK = 0x7f, 114*4882a593Smuzhiyun SR_BUSY = 1 << 0, 115*4882a593Smuzhiyun SR_TF_FULL = 1 << 1, 116*4882a593Smuzhiyun SR_TF_EMPT = 1 << 2, 117*4882a593Smuzhiyun SR_RF_EMPT = 1 << 3, 118*4882a593Smuzhiyun SR_RF_FULL = 1 << 4, 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define ROCKCHIP_SPI_TIMEOUT_MS 1000 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed 125*4882a593Smuzhiyun * hardware limitation... the Linux kernel source has the following 126*4882a593Smuzhiyun * comment: 127*4882a593Smuzhiyun * "sclk_out: spi master internal logic in rk3x can support 50Mhz" 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define ROCKCHIP_SPI_MAX_RATE 50000000 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* __RK_SPI_H */ 132