1 /*
2 * spi driver for rockchip
3 *
4 * (C) Copyright 2015 Google, Inc
5 *
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <clk.h>
14 #include <dm.h>
15 #include <dt-structs.h>
16 #include <errno.h>
17 #include <spi.h>
18 #include <linux/errno.h>
19 #include <asm/io.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/periph.h>
22 #include <dm/pinctrl.h>
23 #include "rk_spi.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /* Change to 1 to output registers at the start of each transaction */
28 #define DEBUG_RK_SPI 0
29
30 struct rockchip_spi_quirks {
31 u32 max_baud_div_in_cpha;
32 };
33
34 struct rockchip_spi_platdata {
35 #if CONFIG_IS_ENABLED(OF_PLATDATA)
36 struct dtd_rockchip_rk3288_spi of_plat;
37 #endif
38 s32 frequency; /* Default clock frequency, -1 for none */
39 fdt_addr_t base;
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
41 uint activate_delay_us; /* Delay to wait after activate */
42 };
43
44 struct rockchip_spi_priv {
45 struct rockchip_spi *regs;
46 struct clk clk;
47 unsigned int max_freq;
48 unsigned int mode;
49 ulong last_transaction_us; /* Time of last transaction end */
50 u8 bits_per_word; /* max 16 bits per word */
51 u8 n_bytes;
52 unsigned int speed_hz;
53 unsigned int last_speed_hz;
54 uint input_rate;
55 uint cr0;
56 u32 rsd; /* Rx sample delay cycles */
57
58 /* quirks */
59 u32 max_baud_div_in_cpha;
60 };
61
62 #define SPI_FIFO_DEPTH 32
63 #define SPI_CR0_RSD_MAX 0x3
64
rkspi_dump_regs(struct rockchip_spi * regs)65 static void rkspi_dump_regs(struct rockchip_spi *regs)
66 {
67 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
68 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
69 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
70 debug("ser: \t\t0x%08x\n", readl(®s->ser));
71 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
72 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
73 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
74 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
75 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
76 debug("sr: \t\t0x%08x\n", readl(®s->sr));
77 debug("imr: \t\t0x%08x\n", readl(®s->imr));
78 debug("isr: \t\t0x%08x\n", readl(®s->isr));
79 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
80 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
81 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
82 }
83
rkspi_enable_chip(struct rockchip_spi * regs,bool enable)84 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
85 {
86 writel(enable ? 1 : 0, ®s->enr);
87 }
88
rkspi_set_clk(struct rockchip_spi_priv * priv,uint speed)89 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
90 {
91 /*
92 * We should try not to exceed the speed requested by the caller:
93 * when selecting a divider, we need to make sure we round up.
94 */
95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
96
97 /* The baudrate register (BAUDR) is defined as a 32bit register where
98 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
99 * 16bits with 'Fsclk_out' defined as follows:
100 *
101 * Fsclk_out = Fspi_clk/ SCKDV
102 * Where SCKDV is any even value between 2 and 65534.
103 */
104 if (clk_div > 0xfffe) {
105 clk_div = 0xfffe;
106 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
107 __func__, speed, priv->input_rate / clk_div);
108 }
109
110 /* Round up to the next even 16bit number */
111 clk_div = (clk_div + 1) & 0xfffe;
112
113 debug("spi speed %u, div %u\n", speed, clk_div);
114
115 /* the maxmum divisor is 4 for mode1/3 spi master case for quirks */
116 if (priv->max_baud_div_in_cpha && clk_div > priv->max_baud_div_in_cpha && priv->mode & SPI_CPHA) {
117 clk_div = priv->max_baud_div_in_cpha;
118 clk_set_rate(&priv->clk, 4 * speed);
119 speed = clk_get_rate(&priv->clk);
120 }
121 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
122 priv->last_speed_hz = speed;
123 }
124
rkspi_wait_till_not_busy(struct rockchip_spi * regs)125 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
126 {
127 unsigned long start;
128
129 start = get_timer(0);
130 while (readl(®s->sr) & SR_BUSY) {
131 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
132 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
133 return -ETIMEDOUT;
134 }
135 }
136
137 return 0;
138 }
139
spi_cs_activate(struct udevice * dev,uint cs)140 static void spi_cs_activate(struct udevice *dev, uint cs)
141 {
142 struct udevice *bus = dev->parent;
143 struct rockchip_spi_platdata *plat = bus->platdata;
144 struct rockchip_spi_priv *priv = dev_get_priv(bus);
145 struct rockchip_spi *regs = priv->regs;
146
147 /* If it's too soon to do another transaction, wait */
148 if (plat->deactivate_delay_us && priv->last_transaction_us) {
149 ulong delay_us; /* The delay completed so far */
150 delay_us = timer_get_us() - priv->last_transaction_us;
151 if (delay_us < plat->deactivate_delay_us)
152 udelay(plat->deactivate_delay_us - delay_us);
153 }
154
155 debug("activate cs%u\n", cs);
156 writel(1 << cs, ®s->ser);
157 if (plat->activate_delay_us)
158 udelay(plat->activate_delay_us);
159 }
160
spi_cs_deactivate(struct udevice * dev,uint cs)161 static void spi_cs_deactivate(struct udevice *dev, uint cs)
162 {
163 struct udevice *bus = dev->parent;
164 struct rockchip_spi_platdata *plat = bus->platdata;
165 struct rockchip_spi_priv *priv = dev_get_priv(bus);
166 struct rockchip_spi *regs = priv->regs;
167
168 debug("deactivate cs%u\n", cs);
169 writel(0, ®s->ser);
170
171 /* Remember time of this transaction so we can honour the bus delay */
172 if (plat->deactivate_delay_us)
173 priv->last_transaction_us = timer_get_us();
174 }
175
176 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_platdata(struct udevice * dev)177 static int conv_of_platdata(struct udevice *dev)
178 {
179 struct rockchip_spi_platdata *plat = dev->platdata;
180 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
181 struct rockchip_spi_priv *priv = dev_get_priv(dev);
182 int ret;
183
184 plat->base = dtplat->reg[0];
185 plat->frequency = 20000000;
186 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
187 if (ret < 0)
188 return ret;
189 dev->req_seq = 0;
190
191 return 0;
192 }
193 #endif
194
rockchip_spi_ofdata_to_platdata(struct udevice * bus)195 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
196 {
197 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
198 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
199 struct rockchip_spi_priv *priv = dev_get_priv(bus);
200 u32 rsd_nsecs;
201 int ret;
202
203 plat->base = dev_read_addr(bus);
204
205 ret = clk_get_by_index(bus, 0, &priv->clk);
206 if (ret < 0) {
207 debug("%s: Could not get clock for %s: %d\n", __func__,
208 bus->name, ret);
209 return ret;
210 }
211
212 plat->frequency =
213 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
214 plat->deactivate_delay_us =
215 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
216 plat->activate_delay_us =
217 dev_read_u32_default(bus, "spi-activate-delay", 0);
218
219 rsd_nsecs = dev_read_u32_default(bus, "rx-sample-delay-ns", 0);
220 if (rsd_nsecs > 0) {
221 u32 spi_clk, rsd;
222
223 spi_clk = clk_get_rate(&priv->clk);
224 /* rx sample delay is expressed in parent clock cycles (max 3) */
225 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (spi_clk >> 8), 1000000000 >> 8);
226 if (!rsd) {
227 pr_err("SPI spi_clk %dHz are too slow to express %u ns delay\n", spi_clk, rsd_nsecs);
228 } else if (rsd > SPI_CR0_RSD_MAX) {
229 rsd = SPI_CR0_RSD_MAX;
230 pr_err("SPI spi_clk %dHz are too fast to express %u ns delay, clamping at %u ns\n",
231 spi_clk, rsd_nsecs, SPI_CR0_RSD_MAX * 1000000000U / spi_clk);
232 }
233 priv->rsd = rsd;
234 }
235
236 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d rsd=%d\n",
237 __func__, (uint)plat->base, plat->frequency,
238 plat->deactivate_delay_us, priv->rsd);
239 #endif
240
241 return 0;
242 }
243
rockchip_spi_calc_modclk(ulong max_freq)244 static int rockchip_spi_calc_modclk(ulong max_freq)
245 {
246 /*
247 * While this is not strictly correct for the RK3368, as the
248 * GPLL will be 576MHz, things will still work, as the
249 * clk_set_rate(...) implementation in our clock-driver will
250 * chose the next closest rate not exceeding what we request
251 * based on the output of this function.
252 */
253
254 unsigned div;
255 const unsigned long gpll_hz = 594000000UL;
256
257 /*
258 * We need to find an input clock that provides at least twice
259 * the maximum frequency and can be generated from the assumed
260 * speed of GPLL (594MHz) using an integer divider.
261 *
262 * To give us more achievable bitrates at higher speeds (these
263 * are generated by dividing by an even 16-bit integer from
264 * this frequency), we try to have an input frequency of at
265 * least 4x our max_freq.
266 */
267
268 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
269 return gpll_hz / div;
270 }
271
rockchip_spi_probe(struct udevice * bus)272 static int rockchip_spi_probe(struct udevice *bus)
273 {
274 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
275 struct rockchip_spi_priv *priv = dev_get_priv(bus);
276 struct rockchip_spi_quirks *quirks_cfg;
277 int ret;
278
279 debug("%s: probe\n", __func__);
280 #if CONFIG_IS_ENABLED(OF_PLATDATA)
281 ret = conv_of_platdata(bus);
282 if (ret)
283 return ret;
284 #endif
285 priv->regs = (struct rockchip_spi *)plat->base;
286
287 priv->last_transaction_us = timer_get_us();
288 priv->max_freq = plat->frequency;
289
290 /* Clamp the value from the DTS against any hardware limits */
291 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
292 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
293
294 /* Find a module-input clock that fits with the max_freq setting */
295 ret = clk_set_rate(&priv->clk,
296 rockchip_spi_calc_modclk(priv->max_freq));
297 if (ret < 0) {
298 debug("%s: Failed to set clock: %d\n", __func__, ret);
299 return ret;
300 }
301 priv->input_rate = ret;
302 debug("%s: rate = %u\n", __func__, priv->input_rate);
303 priv->bits_per_word = 8;
304 quirks_cfg = (struct rockchip_spi_quirks *)dev_get_driver_data(bus);
305 if (quirks_cfg)
306 priv->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha;
307
308 return 0;
309 }
310
rockchip_spi_claim_bus(struct udevice * dev)311 static int rockchip_spi_claim_bus(struct udevice *dev)
312 {
313 struct udevice *bus = dev->parent;
314 struct rockchip_spi_priv *priv = dev_get_priv(bus);
315 struct rockchip_spi *regs = priv->regs;
316 u8 spi_dfs, spi_tf;
317 uint ctrlr0;
318
319 /* Disable the SPI hardware */
320 rkspi_enable_chip(regs, 0);
321
322 switch (priv->bits_per_word) {
323 case 8:
324 priv->n_bytes = 1;
325 spi_dfs = DFS_8BIT;
326 spi_tf = HALF_WORD_OFF;
327 break;
328 case 16:
329 priv->n_bytes = 2;
330 spi_dfs = DFS_16BIT;
331 spi_tf = HALF_WORD_ON;
332 break;
333 default:
334 debug("%s: unsupported bits: %dbits\n", __func__,
335 priv->bits_per_word);
336 return -EPROTONOSUPPORT;
337 }
338
339 if (priv->speed_hz != priv->last_speed_hz)
340 rkspi_set_clk(priv, priv->speed_hz);
341
342 /* Operation Mode */
343 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
344
345 /* Data Frame Size */
346 ctrlr0 |= spi_dfs << DFS_SHIFT;
347
348 /* set SPI mode 0..3 */
349 if (priv->mode & SPI_CPOL)
350 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
351 if (priv->mode & SPI_CPHA)
352 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
353
354 /* Chip Select Mode */
355 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
356
357 /* SSN to Sclk_out delay */
358 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
359
360 /* Serial Endian Mode */
361 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
362
363 /* First Bit Mode */
364 ctrlr0 |= FBM_MSB << FBM_SHIFT;
365
366 /* Byte and Halfword Transform */
367 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
368
369 /* Rxd Sample Delay */
370 ctrlr0 |= priv->rsd << RXDSD_SHIFT;
371
372 /* Frame Format */
373 ctrlr0 |= FRF_SPI << FRF_SHIFT;
374
375 /* Save static configuration */
376 priv->cr0 = ctrlr0;
377
378 writel(ctrlr0, ®s->ctrlr0);
379
380 return 0;
381 }
382
rockchip_spi_config(struct rockchip_spi_priv * priv,const void * dout)383 static int rockchip_spi_config(struct rockchip_spi_priv *priv, const void *dout)
384 {
385 struct rockchip_spi *regs = priv->regs;
386 uint ctrlr0 = priv->cr0;
387 u32 tmod;
388
389 if (dout)
390 tmod = TMOD_TR;
391 else
392 tmod = TMOD_RO;
393
394 ctrlr0 |= (tmod & TMOD_MASK) << TMOD_SHIFT;
395 writel(ctrlr0, ®s->ctrlr0);
396
397 return 0;
398 }
399
rockchip_spi_release_bus(struct udevice * dev)400 static int rockchip_spi_release_bus(struct udevice *dev)
401 {
402 struct udevice *bus = dev->parent;
403 struct rockchip_spi_priv *priv = dev_get_priv(bus);
404
405 rkspi_enable_chip(priv->regs, false);
406
407 return 0;
408 }
409
rockchip_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)410 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
411 const void *dout, void *din, unsigned long flags)
412 {
413 struct udevice *bus = dev->parent;
414 struct rockchip_spi_priv *priv = dev_get_priv(bus);
415 struct rockchip_spi *regs = priv->regs;
416 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
417 int len = bitlen >> 3;
418 const u8 *out = dout;
419 u8 *in = din;
420 int toread, towrite;
421 int ret;
422
423 rockchip_spi_config(priv, dout);
424
425 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
426 len, flags);
427 if (DEBUG_RK_SPI)
428 rkspi_dump_regs(regs);
429
430 /* Assert CS before transfer */
431 if (flags & SPI_XFER_BEGIN)
432 spi_cs_activate(dev, slave_plat->cs);
433
434 while (len > 0) {
435 int todo = min(len, 0xffff);
436
437 rkspi_enable_chip(regs, false);
438 writel(todo - 1, ®s->ctrlr1);
439 rkspi_enable_chip(regs, true);
440
441 toread = todo;
442 towrite = todo;
443 while (toread || towrite) {
444 u32 status = readl(®s->sr);
445
446 if (towrite && !(status & SR_TF_FULL)) {
447 if (out)
448 writel(out ? *out++ : 0, regs->txdr);
449 towrite--;
450 }
451 if (toread && !(status & SR_RF_EMPT)) {
452 u32 byte = readl(regs->rxdr);
453
454 if (in)
455 *in++ = byte;
456 toread--;
457 }
458 }
459 ret = rkspi_wait_till_not_busy(regs);
460 if (ret)
461 break;
462 len -= todo;
463 }
464
465 /* Deassert CS after transfer */
466 if (flags & SPI_XFER_END)
467 spi_cs_deactivate(dev, slave_plat->cs);
468
469 rkspi_enable_chip(regs, false);
470
471 return ret;
472 }
473
rockchip_spi_set_speed(struct udevice * bus,uint speed)474 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
475 {
476 struct rockchip_spi_priv *priv = dev_get_priv(bus);
477
478 /* Clamp to the maximum frequency specified in the DTS */
479 if (speed > priv->max_freq)
480 speed = priv->max_freq;
481
482 priv->speed_hz = speed;
483
484 return 0;
485 }
486
rockchip_spi_set_mode(struct udevice * bus,uint mode)487 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
488 {
489 struct rockchip_spi_priv *priv = dev_get_priv(bus);
490
491 priv->mode = mode;
492
493 return 0;
494 }
495
496 static const struct dm_spi_ops rockchip_spi_ops = {
497 .claim_bus = rockchip_spi_claim_bus,
498 .release_bus = rockchip_spi_release_bus,
499 .xfer = rockchip_spi_xfer,
500 .set_speed = rockchip_spi_set_speed,
501 .set_mode = rockchip_spi_set_mode,
502 /*
503 * cs_info is not needed, since we require all chip selects to be
504 * in the device tree explicitly
505 */
506 };
507
508 static const struct rockchip_spi_quirks rockchip_spi_quirks_cfg = {
509 .max_baud_div_in_cpha = 4,
510 };
511
512 static const struct udevice_id rockchip_spi_ids[] = {
513 {
514 .compatible = "rockchip,px30-spi",
515 .data = (ulong)&rockchip_spi_quirks_cfg,
516 },
517 { .compatible = "rockchip,rk3288-spi" },
518 { .compatible = "rockchip,rk3368-spi" },
519 { .compatible = "rockchip,rk3399-spi" },
520 { .compatible = "rockchip,rk3066-spi" },
521 { .compatible = "rockchip,rk3328-spi" },
522 { }
523 };
524
525 U_BOOT_DRIVER(rockchip_spi) = {
526 #if CONFIG_IS_ENABLED(OF_PLATDATA)
527 .name = "rockchip_rk3288_spi",
528 #else
529 .name = "rockchip_spi",
530 #endif
531 .id = UCLASS_SPI,
532 .of_match = rockchip_spi_ids,
533 .ops = &rockchip_spi_ops,
534 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
535 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
536 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
537 .probe = rockchip_spi_probe,
538 };
539