1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
3*4882a593Smuzhiyun * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <spi.h>
12*4882a593Smuzhiyun #include <asm/mpc8xxx_spi.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
15*4882a593Smuzhiyun #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
18*4882a593Smuzhiyun #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
19*4882a593Smuzhiyun #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
20*4882a593Smuzhiyun #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SPI_TIMEOUT 1000
23*4882a593Smuzhiyun
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)24*4882a593Smuzhiyun struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
25*4882a593Smuzhiyun unsigned int max_hz, unsigned int mode)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct spi_slave *slave;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (!spi_cs_is_valid(bus, cs))
30*4882a593Smuzhiyun return NULL;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun slave = spi_alloc_slave_base(bus, cs);
33*4882a593Smuzhiyun if (!slave)
34*4882a593Smuzhiyun return NULL;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * TODO: Some of the code in spi_init() should probably move
38*4882a593Smuzhiyun * here, or into spi_claim_bus() below.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return slave;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
spi_free_slave(struct spi_slave * slave)44*4882a593Smuzhiyun void spi_free_slave(struct spi_slave *slave)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun free(slave);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
spi_init(void)49*4882a593Smuzhiyun void spi_init(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * SPI pins on the MPC83xx are not muxed, so all we do is initialize
55*4882a593Smuzhiyun * some registers
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
58*4882a593Smuzhiyun spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
59*4882a593Smuzhiyun (16.67MHz typ.) */
60*4882a593Smuzhiyun spi->event = 0xffffffff; /* Clear all SPI events */
61*4882a593Smuzhiyun spi->mask = 0x00000000; /* Mask all SPI interrupts */
62*4882a593Smuzhiyun spi->com = 0; /* LST bit doesn't do anything, so disregard */
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
spi_claim_bus(struct spi_slave * slave)65*4882a593Smuzhiyun int spi_claim_bus(struct spi_slave *slave)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
spi_release_bus(struct spi_slave * slave)70*4882a593Smuzhiyun void spi_release_bus(struct spi_slave *slave)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)75*4882a593Smuzhiyun int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
76*4882a593Smuzhiyun void *din, unsigned long flags)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
79*4882a593Smuzhiyun unsigned int tmpdout, tmpdin, event;
80*4882a593Smuzhiyun int numBlks = DIV_ROUND_UP(bitlen, 32);
81*4882a593Smuzhiyun int tm, isRead = 0;
82*4882a593Smuzhiyun unsigned char charSize = 32;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
85*4882a593Smuzhiyun slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (flags & SPI_XFER_BEGIN)
88*4882a593Smuzhiyun spi_cs_activate(slave);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun spi->event = 0xffffffff; /* Clear all SPI events */
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* handle data in 32-bit chunks */
93*4882a593Smuzhiyun while (numBlks--) {
94*4882a593Smuzhiyun tmpdout = 0;
95*4882a593Smuzhiyun charSize = (bitlen >= 32 ? 32 : bitlen);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Shift data so it's msb-justified */
98*4882a593Smuzhiyun tmpdout = *(u32 *) dout >> (32 - charSize);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* The LEN field of the SPMODE register is set as follows:
101*4882a593Smuzhiyun *
102*4882a593Smuzhiyun * Bit length setting
103*4882a593Smuzhiyun * len <= 4 3
104*4882a593Smuzhiyun * 4 < len <= 16 len - 1
105*4882a593Smuzhiyun * len > 16 0
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun spi->mode &= ~SPI_MODE_EN;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (bitlen <= 16) {
111*4882a593Smuzhiyun if (bitlen <= 4)
112*4882a593Smuzhiyun spi->mode = (spi->mode & 0xff0fffff) |
113*4882a593Smuzhiyun (3 << 20);
114*4882a593Smuzhiyun else
115*4882a593Smuzhiyun spi->mode = (spi->mode & 0xff0fffff) |
116*4882a593Smuzhiyun ((bitlen - 1) << 20);
117*4882a593Smuzhiyun } else {
118*4882a593Smuzhiyun spi->mode = (spi->mode & 0xff0fffff);
119*4882a593Smuzhiyun /* Set up the next iteration if sending > 32 bits */
120*4882a593Smuzhiyun bitlen -= 32;
121*4882a593Smuzhiyun dout += 4;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun spi->mode |= SPI_MODE_EN;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun spi->tx = tmpdout; /* Write the data out */
127*4882a593Smuzhiyun debug("*** spi_xfer: ... %08x written\n", tmpdout);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Wait for SPI transmit to get out
131*4882a593Smuzhiyun * or time out (1 second = 1000 ms)
132*4882a593Smuzhiyun * The NE event must be read and cleared first
133*4882a593Smuzhiyun */
134*4882a593Smuzhiyun for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
135*4882a593Smuzhiyun event = spi->event;
136*4882a593Smuzhiyun if (event & SPI_EV_NE) {
137*4882a593Smuzhiyun tmpdin = spi->rx;
138*4882a593Smuzhiyun spi->event |= SPI_EV_NE;
139*4882a593Smuzhiyun isRead = 1;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun *(u32 *) din = (tmpdin << (32 - charSize));
142*4882a593Smuzhiyun if (charSize == 32) {
143*4882a593Smuzhiyun /* Advance output buffer by 32 bits */
144*4882a593Smuzhiyun din += 4;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * Only bail when we've had both NE and NF events.
149*4882a593Smuzhiyun * This will cause timeouts on RO devices, so maybe
150*4882a593Smuzhiyun * in the future put an arbitrary delay after writing
151*4882a593Smuzhiyun * the device. Arbitrary delays suck, though...
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun if (isRead && (event & SPI_EV_NF))
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun if (tm >= SPI_TIMEOUT)
157*4882a593Smuzhiyun puts("*** spi_xfer: Time out during SPI transfer");
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun if (flags & SPI_XFER_END)
163*4882a593Smuzhiyun spi_cs_deactivate(slave);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun }
167