1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * LPC32xx SSP interface (SPI mode)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2014 DENX Software Engineering GmbH
5*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <linux/compat.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <malloc.h>
14*4882a593Smuzhiyun #include <spi.h>
15*4882a593Smuzhiyun #include <asm/arch/clk.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* SSP chip registers */
18*4882a593Smuzhiyun struct ssp_regs {
19*4882a593Smuzhiyun u32 cr0;
20*4882a593Smuzhiyun u32 cr1;
21*4882a593Smuzhiyun u32 data;
22*4882a593Smuzhiyun u32 sr;
23*4882a593Smuzhiyun u32 cpsr;
24*4882a593Smuzhiyun u32 imsc;
25*4882a593Smuzhiyun u32 ris;
26*4882a593Smuzhiyun u32 mis;
27*4882a593Smuzhiyun u32 icr;
28*4882a593Smuzhiyun u32 dmacr;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* CR1 register defines */
32*4882a593Smuzhiyun #define SSP_CR1_SSP_ENABLE 0x0002
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* SR register defines */
35*4882a593Smuzhiyun #define SSP_SR_TNF 0x0002
36*4882a593Smuzhiyun /* SSP status RX FIFO not empty bit */
37*4882a593Smuzhiyun #define SSP_SR_RNE 0x0004
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* lpc32xx spi slave */
40*4882a593Smuzhiyun struct lpc32xx_spi_slave {
41*4882a593Smuzhiyun struct spi_slave slave;
42*4882a593Smuzhiyun struct ssp_regs *regs;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
to_lpc32xx_spi_slave(struct spi_slave * slave)45*4882a593Smuzhiyun static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
46*4882a593Smuzhiyun struct spi_slave *slave)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun return container_of(slave, struct lpc32xx_spi_slave, slave);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* spi_init is called during boot when CONFIG_CMD_SPI is defined */
spi_init(void)52*4882a593Smuzhiyun void spi_init(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * nothing to do: clocking was enabled in lpc32xx_ssp_enable()
56*4882a593Smuzhiyun * and configuration will be done in spi_setup_slave()
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* the following is called in sequence by do_spi_xfer() */
61*4882a593Smuzhiyun
spi_setup_slave(uint bus,uint cs,uint max_hz,uint mode)62*4882a593Smuzhiyun struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct lpc32xx_spi_slave *lslave;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* we only set up SSP0 for now, so ignore bus */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (mode & SPI_3WIRE) {
69*4882a593Smuzhiyun pr_err("3-wire mode not supported");
70*4882a593Smuzhiyun return NULL;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (mode & SPI_SLAVE) {
74*4882a593Smuzhiyun pr_err("slave mode not supported\n");
75*4882a593Smuzhiyun return NULL;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (mode & SPI_PREAMBLE) {
79*4882a593Smuzhiyun pr_err("preamble byte skipping not supported\n");
80*4882a593Smuzhiyun return NULL;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs);
84*4882a593Smuzhiyun if (!lslave) {
85*4882a593Smuzhiyun printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n");
86*4882a593Smuzhiyun return NULL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun lslave->regs = (struct ssp_regs *)SSP0_BASE;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
93*4882a593Smuzhiyun * Set SCR to 0 and CPSDVSR to 26.
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
97*4882a593Smuzhiyun writel(26, &lslave->regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
98*4882a593Smuzhiyun writel(0, &lslave->regs->imsc); /* do not raise any interrupts */
99*4882a593Smuzhiyun writel(0, &lslave->regs->icr); /* clear any pending interrupt */
100*4882a593Smuzhiyun writel(0, &lslave->regs->dmacr); /* do not do DMAs */
101*4882a593Smuzhiyun writel(SSP_CR1_SSP_ENABLE, &lslave->regs->cr1); /* enable SSP0 */
102*4882a593Smuzhiyun return &lslave->slave;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
spi_free_slave(struct spi_slave * slave)105*4882a593Smuzhiyun void spi_free_slave(struct spi_slave *slave)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave);
110*4882a593Smuzhiyun free(lslave);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
spi_claim_bus(struct spi_slave * slave)113*4882a593Smuzhiyun int spi_claim_bus(struct spi_slave *slave)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun /* only one bus and slave so far, always available */
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)119*4882a593Smuzhiyun int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
120*4882a593Smuzhiyun const void *dout, void *din, unsigned long flags)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave);
123*4882a593Smuzhiyun int bytelen = bitlen >> 3;
124*4882a593Smuzhiyun int idx_out = 0;
125*4882a593Smuzhiyun int idx_in = 0;
126*4882a593Smuzhiyun int start_time;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun start_time = get_timer(0);
129*4882a593Smuzhiyun while ((idx_out < bytelen) || (idx_in < bytelen)) {
130*4882a593Smuzhiyun int status = readl(&lslave->regs->sr);
131*4882a593Smuzhiyun if ((idx_out < bytelen) && (status & SSP_SR_TNF))
132*4882a593Smuzhiyun writel(((u8 *)dout)[idx_out++], &lslave->regs->data);
133*4882a593Smuzhiyun if ((idx_in < bytelen) && (status & status & SSP_SR_RNE))
134*4882a593Smuzhiyun ((u8 *)din)[idx_in++] = readl(&lslave->regs->data);
135*4882a593Smuzhiyun if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT)
136*4882a593Smuzhiyun return -1;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
spi_release_bus(struct spi_slave * slave)141*4882a593Smuzhiyun void spi_release_bus(struct spi_slave *slave)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun /* do nothing */
144*4882a593Smuzhiyun }
145