1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <linux/errno.h>
31 #include <wait_bit.h>
32 #include <spi.h>
33 #include "cadence_qspi.h"
34
35 #define CQSPI_REG_POLL_US 1 /* 1us */
36 #define CQSPI_REG_RETRY 10000
37 #define CQSPI_POLL_IDLE_RETRY 3
38
39 /* Transfer mode */
40 #define CQSPI_INST_TYPE_SINGLE 0
41 #define CQSPI_INST_TYPE_DUAL 1
42 #define CQSPI_INST_TYPE_QUAD 2
43
44 #define CQSPI_STIG_DATA_LEN_MAX 8
45
46 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
47 #define CQSPI_DUMMY_BYTES_MAX 4
48
49 /****************************************************************************
50 * Controller's configuration and status register (offset from QSPI_BASE)
51 ****************************************************************************/
52 #define CQSPI_REG_CONFIG 0x00
53 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
54 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
55 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
56 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
57 #define CQSPI_REG_CONFIG_DECODE BIT(9)
58 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
59 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
60 #define CQSPI_REG_CONFIG_BAUD_LSB 19
61 #define CQSPI_REG_CONFIG_IDLE_LSB 31
62 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
63 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
64
65 #define CQSPI_REG_RD_INSTR 0x04
66 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
67 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
68 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
69 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
70 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
71 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
72 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
73 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
74 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
75 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
76
77 #define CQSPI_REG_WR_INSTR 0x08
78 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
79
80 #define CQSPI_REG_DELAY 0x0C
81 #define CQSPI_REG_DELAY_TSLCH_LSB 0
82 #define CQSPI_REG_DELAY_TCHSH_LSB 8
83 #define CQSPI_REG_DELAY_TSD2D_LSB 16
84 #define CQSPI_REG_DELAY_TSHSL_LSB 24
85 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
86 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
87 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
88 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
89
90 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
91 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
92 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
93 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
94
95 #define CQSPI_REG_SIZE 0x14
96 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
97 #define CQSPI_REG_SIZE_PAGE_LSB 4
98 #define CQSPI_REG_SIZE_BLOCK_LSB 16
99 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
100 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
101 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
102
103 #define CQSPI_REG_SRAMPARTITION 0x18
104 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
105
106 #define CQSPI_REG_REMAP 0x24
107 #define CQSPI_REG_MODE_BIT 0x28
108
109 #define CQSPI_REG_SDRAMLEVEL 0x2C
110 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
111 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
112 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
113 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
114
115 #define CQSPI_REG_IRQSTATUS 0x40
116 #define CQSPI_REG_IRQMASK 0x44
117
118 #define CQSPI_REG_INDIRECTRD 0x60
119 #define CQSPI_REG_INDIRECTRD_START BIT(0)
120 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
121 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
122 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
123
124 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
125 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
126 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
127
128 #define CQSPI_REG_CMDCTRL 0x90
129 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
130 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
131 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
132 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
133 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
134 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
135 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
136 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
137 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
138 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
139 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
140 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
142 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
143 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
144
145 #define CQSPI_REG_INDIRECTWR 0x70
146 #define CQSPI_REG_INDIRECTWR_START BIT(0)
147 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
148 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
149 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
150
151 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
152 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
153 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
154
155 #define CQSPI_REG_CMDADDRESS 0x94
156 #define CQSPI_REG_CMDREADDATALOWER 0xA0
157 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
158 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
159 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
160
161 #define CQSPI_REG_IS_IDLE(base) \
162 ((readl(base + CQSPI_REG_CONFIG) >> \
163 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
164
165 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
166 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
167 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
168
169 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
170 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
171 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
172
cadence_qspi_apb_cmd2addr(const unsigned char * addr_buf,unsigned int addr_width)173 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
174 unsigned int addr_width)
175 {
176 unsigned int addr;
177
178 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
179
180 if (addr_width == 4)
181 addr = (addr << 8) | addr_buf[3];
182
183 return addr;
184 }
185
cadence_qspi_apb_controller_enable(void * reg_base)186 void cadence_qspi_apb_controller_enable(void *reg_base)
187 {
188 unsigned int reg;
189 reg = readl(reg_base + CQSPI_REG_CONFIG);
190 reg |= CQSPI_REG_CONFIG_ENABLE;
191 writel(reg, reg_base + CQSPI_REG_CONFIG);
192 }
193
cadence_qspi_apb_controller_disable(void * reg_base)194 void cadence_qspi_apb_controller_disable(void *reg_base)
195 {
196 unsigned int reg;
197 reg = readl(reg_base + CQSPI_REG_CONFIG);
198 reg &= ~CQSPI_REG_CONFIG_ENABLE;
199 writel(reg, reg_base + CQSPI_REG_CONFIG);
200 }
201
202 /* Return 1 if idle, otherwise return 0 (busy). */
cadence_qspi_wait_idle(void * reg_base)203 static unsigned int cadence_qspi_wait_idle(void *reg_base)
204 {
205 unsigned int start, count = 0;
206 /* timeout in unit of ms */
207 unsigned int timeout = 5000;
208
209 start = get_timer(0);
210 for ( ; get_timer(start) < timeout ; ) {
211 if (CQSPI_REG_IS_IDLE(reg_base))
212 count++;
213 else
214 count = 0;
215 /*
216 * Ensure the QSPI controller is in true idle state after
217 * reading back the same idle status consecutively
218 */
219 if (count >= CQSPI_POLL_IDLE_RETRY)
220 return 1;
221 }
222
223 /* Timeout, still in busy mode. */
224 printf("QSPI: QSPI is still busy after poll for %d times.\n",
225 CQSPI_REG_RETRY);
226 return 0;
227 }
228
cadence_qspi_apb_readdata_capture(void * reg_base,unsigned int bypass,unsigned int delay)229 void cadence_qspi_apb_readdata_capture(void *reg_base,
230 unsigned int bypass, unsigned int delay)
231 {
232 unsigned int reg;
233 cadence_qspi_apb_controller_disable(reg_base);
234
235 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
236
237 if (bypass)
238 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
239 else
240 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
241
242 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
243 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
244
245 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
246 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
247
248 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
249
250 cadence_qspi_apb_controller_enable(reg_base);
251 }
252
cadence_qspi_apb_config_baudrate_div(void * reg_base,unsigned int ref_clk_hz,unsigned int sclk_hz)253 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
254 unsigned int ref_clk_hz, unsigned int sclk_hz)
255 {
256 unsigned int reg;
257 unsigned int div;
258
259 cadence_qspi_apb_controller_disable(reg_base);
260 reg = readl(reg_base + CQSPI_REG_CONFIG);
261 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
262
263 /*
264 * The baud_div field in the config reg is 4 bits, and the ref clock is
265 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
266 * SPI clock rate is less than or equal to the requested clock rate.
267 */
268 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
269
270 /* ensure the baud rate doesn't exceed the max value */
271 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
272 div = CQSPI_REG_CONFIG_BAUD_MASK;
273
274 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
275 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
276
277 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
278 writel(reg, reg_base + CQSPI_REG_CONFIG);
279
280 cadence_qspi_apb_controller_enable(reg_base);
281 }
282
cadence_qspi_apb_set_clk_mode(void * reg_base,uint mode)283 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
284 {
285 unsigned int reg;
286
287 cadence_qspi_apb_controller_disable(reg_base);
288 reg = readl(reg_base + CQSPI_REG_CONFIG);
289 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
290
291 if (mode & SPI_CPOL)
292 reg |= CQSPI_REG_CONFIG_CLK_POL;
293 if (mode & SPI_CPHA)
294 reg |= CQSPI_REG_CONFIG_CLK_PHA;
295
296 writel(reg, reg_base + CQSPI_REG_CONFIG);
297
298 cadence_qspi_apb_controller_enable(reg_base);
299 }
300
cadence_qspi_apb_chipselect(void * reg_base,unsigned int chip_select,unsigned int decoder_enable)301 void cadence_qspi_apb_chipselect(void *reg_base,
302 unsigned int chip_select, unsigned int decoder_enable)
303 {
304 unsigned int reg;
305
306 cadence_qspi_apb_controller_disable(reg_base);
307
308 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
309 decoder_enable);
310
311 reg = readl(reg_base + CQSPI_REG_CONFIG);
312 /* docoder */
313 if (decoder_enable) {
314 reg |= CQSPI_REG_CONFIG_DECODE;
315 } else {
316 reg &= ~CQSPI_REG_CONFIG_DECODE;
317 /* Convert CS if without decoder.
318 * CS0 to 4b'1110
319 * CS1 to 4b'1101
320 * CS2 to 4b'1011
321 * CS3 to 4b'0111
322 */
323 chip_select = 0xF & ~(1 << chip_select);
324 }
325
326 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
327 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
328 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
329 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
330 writel(reg, reg_base + CQSPI_REG_CONFIG);
331
332 cadence_qspi_apb_controller_enable(reg_base);
333 }
334
cadence_qspi_apb_delay(void * reg_base,unsigned int ref_clk,unsigned int sclk_hz,unsigned int tshsl_ns,unsigned int tsd2d_ns,unsigned int tchsh_ns,unsigned int tslch_ns)335 void cadence_qspi_apb_delay(void *reg_base,
336 unsigned int ref_clk, unsigned int sclk_hz,
337 unsigned int tshsl_ns, unsigned int tsd2d_ns,
338 unsigned int tchsh_ns, unsigned int tslch_ns)
339 {
340 unsigned int ref_clk_ns;
341 unsigned int sclk_ns;
342 unsigned int tshsl, tchsh, tslch, tsd2d;
343 unsigned int reg;
344
345 cadence_qspi_apb_controller_disable(reg_base);
346
347 /* Convert to ns. */
348 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
349
350 /* Convert to ns. */
351 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
352
353 /* The controller adds additional delay to that programmed in the reg */
354 if (tshsl_ns >= sclk_ns + ref_clk_ns)
355 tshsl_ns -= sclk_ns + ref_clk_ns;
356 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
357 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
358 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
359 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
360 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
361 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
362
363 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
364 << CQSPI_REG_DELAY_TSHSL_LSB);
365 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
366 << CQSPI_REG_DELAY_TCHSH_LSB);
367 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
368 << CQSPI_REG_DELAY_TSLCH_LSB);
369 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
370 << CQSPI_REG_DELAY_TSD2D_LSB);
371 writel(reg, reg_base + CQSPI_REG_DELAY);
372
373 cadence_qspi_apb_controller_enable(reg_base);
374 }
375
cadence_qspi_apb_controller_init(struct cadence_spi_platdata * plat)376 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
377 {
378 unsigned reg;
379
380 cadence_qspi_apb_controller_disable(plat->regbase);
381
382 /* Configure the device size and address bytes */
383 reg = readl(plat->regbase + CQSPI_REG_SIZE);
384 /* Clear the previous value */
385 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
386 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
387 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
388 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
389 writel(reg, plat->regbase + CQSPI_REG_SIZE);
390
391 /* Configure the remap address register, no remap */
392 writel(0, plat->regbase + CQSPI_REG_REMAP);
393
394 /* Indirect mode configurations */
395 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
396
397 /* Disable all interrupts */
398 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
399
400 cadence_qspi_apb_controller_enable(plat->regbase);
401 }
402
cadence_qspi_apb_exec_flash_cmd(void * reg_base,unsigned int reg)403 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
404 unsigned int reg)
405 {
406 unsigned int retry = CQSPI_REG_RETRY;
407
408 /* Write the CMDCTRL without start execution. */
409 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
410 /* Start execute */
411 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
412 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
413
414 while (retry--) {
415 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
416 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
417 break;
418 udelay(1);
419 }
420
421 if (!retry) {
422 printf("QSPI: flash command execution timeout\n");
423 return -EIO;
424 }
425
426 /* Polling QSPI idle status. */
427 if (!cadence_qspi_wait_idle(reg_base))
428 return -EIO;
429
430 return 0;
431 }
432
433 /* For command RDID, RDSR. */
cadence_qspi_apb_command_read(void * reg_base,unsigned int cmdlen,const u8 * cmdbuf,unsigned int rxlen,u8 * rxbuf)434 int cadence_qspi_apb_command_read(void *reg_base,
435 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
436 u8 *rxbuf)
437 {
438 unsigned int reg;
439 unsigned int read_len;
440 int status;
441
442 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
443 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
444 cmdlen, rxlen);
445 return -EINVAL;
446 }
447
448 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
449
450 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
451
452 /* 0 means 1 byte. */
453 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
454 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
455 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
456 if (status != 0)
457 return status;
458
459 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
460
461 /* Put the read value into rx_buf */
462 read_len = (rxlen > 4) ? 4 : rxlen;
463 memcpy(rxbuf, ®, read_len);
464 rxbuf += read_len;
465
466 if (rxlen > 4) {
467 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
468
469 read_len = rxlen - read_len;
470 memcpy(rxbuf, ®, read_len);
471 }
472 return 0;
473 }
474
475 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
cadence_qspi_apb_command_write(void * reg_base,unsigned int cmdlen,const u8 * cmdbuf,unsigned int txlen,const u8 * txbuf)476 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
477 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
478 {
479 unsigned int reg = 0;
480 unsigned int addr_value;
481 unsigned int wr_data;
482 unsigned int wr_len;
483
484 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
485 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
486 cmdlen, txlen);
487 return -EINVAL;
488 }
489
490 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
491
492 if (cmdlen == 4 || cmdlen == 5) {
493 /* Command with address */
494 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
495 /* Number of bytes to write. */
496 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
497 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
498 /* Get address */
499 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
500 cmdlen >= 5 ? 4 : 3);
501
502 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
503 }
504
505 if (txlen) {
506 /* writing data = yes */
507 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
508 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
509 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
510
511 wr_len = txlen > 4 ? 4 : txlen;
512 memcpy(&wr_data, txbuf, wr_len);
513 writel(wr_data, reg_base +
514 CQSPI_REG_CMDWRITEDATALOWER);
515
516 if (txlen > 4) {
517 txbuf += wr_len;
518 wr_len = txlen - wr_len;
519 memcpy(&wr_data, txbuf, wr_len);
520 writel(wr_data, reg_base +
521 CQSPI_REG_CMDWRITEDATAUPPER);
522 }
523 }
524
525 /* Execute the command */
526 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
527 }
528
529 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata * plat,unsigned int cmdlen,unsigned int rx_width,const u8 * cmdbuf)530 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
531 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
532 {
533 unsigned int reg;
534 unsigned int rd_reg;
535 unsigned int addr_value;
536 unsigned int dummy_clk;
537 unsigned int dummy_bytes;
538 unsigned int addr_bytes;
539
540 /*
541 * Identify addr_byte. All NOR flash device drivers are using fast read
542 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
543 * With that, the length is in value of 5 or 6. Only FRAM chip from
544 * ramtron using normal read (which won't need dummy byte).
545 * Unlikely NOR flash using normal read due to performance issue.
546 */
547 if (cmdlen >= 5)
548 /* to cater fast read where cmd + addr + dummy */
549 addr_bytes = cmdlen - 2;
550 else
551 /* for normal read (only ramtron as of now) */
552 addr_bytes = cmdlen - 1;
553
554 /* Setup the indirect trigger address */
555 writel(plat->trigger_address,
556 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
557
558 /* Configure the opcode */
559 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
560
561 if (rx_width & SPI_RX_QUAD)
562 /* Instruction and address at DQ0, data at DQ0-3. */
563 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
564
565 /* Get address */
566 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
567 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
568
569 /* The remaining lenght is dummy bytes. */
570 dummy_bytes = cmdlen - addr_bytes - 1;
571 if (dummy_bytes) {
572 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
573 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
574
575 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
576 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
577 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
578 #else
579 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
580 #endif
581
582 /* Convert to clock cycles. */
583 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
584 /* Need to minus the mode byte (8 clocks). */
585 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
586
587 if (dummy_clk)
588 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
589 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
590 }
591
592 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
593
594 /* set device size */
595 reg = readl(plat->regbase + CQSPI_REG_SIZE);
596 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
597 reg |= (addr_bytes - 1);
598 writel(reg, plat->regbase + CQSPI_REG_SIZE);
599 return 0;
600 }
601
cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata * plat)602 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
603 {
604 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
605 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
606 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
607 }
608
cadence_qspi_wait_for_data(struct cadence_spi_platdata * plat)609 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
610 {
611 unsigned int timeout = 10000;
612 u32 reg;
613
614 while (timeout--) {
615 reg = cadence_qspi_get_rd_sram_level(plat);
616 if (reg)
617 return reg;
618 udelay(1);
619 }
620
621 return -ETIMEDOUT;
622 }
623
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata * plat,unsigned int n_rx,u8 * rxbuf)624 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
625 unsigned int n_rx, u8 *rxbuf)
626 {
627 unsigned int remaining = n_rx;
628 unsigned int bytes_to_read = 0;
629 int ret;
630
631 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
632
633 /* Start the indirect read transfer */
634 writel(CQSPI_REG_INDIRECTRD_START,
635 plat->regbase + CQSPI_REG_INDIRECTRD);
636
637 while (remaining > 0) {
638 ret = cadence_qspi_wait_for_data(plat);
639 if (ret < 0) {
640 printf("Indirect write timed out (%i)\n", ret);
641 goto failrd;
642 }
643
644 bytes_to_read = ret;
645
646 while (bytes_to_read != 0) {
647 bytes_to_read *= plat->fifo_width;
648 bytes_to_read = bytes_to_read > remaining ?
649 remaining : bytes_to_read;
650 /*
651 * Handle non-4-byte aligned access to avoid
652 * data abort.
653 */
654 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
655 readsb(plat->ahbbase, rxbuf, bytes_to_read);
656 else
657 readsl(plat->ahbbase, rxbuf,
658 bytes_to_read >> 2);
659 rxbuf += bytes_to_read;
660 remaining -= bytes_to_read;
661 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
662 }
663 }
664
665 /* Check indirect done status */
666 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
667 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
668 if (ret) {
669 printf("Indirect read completion error (%i)\n", ret);
670 goto failrd;
671 }
672
673 /* Clear indirect completion status */
674 writel(CQSPI_REG_INDIRECTRD_DONE,
675 plat->regbase + CQSPI_REG_INDIRECTRD);
676
677 return 0;
678
679 failrd:
680 /* Cancel the indirect read */
681 writel(CQSPI_REG_INDIRECTRD_CANCEL,
682 plat->regbase + CQSPI_REG_INDIRECTRD);
683 return ret;
684 }
685
686 /* Opcode + Address (3/4 bytes) */
cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata * plat,unsigned int cmdlen,const u8 * cmdbuf)687 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
688 unsigned int cmdlen, const u8 *cmdbuf)
689 {
690 unsigned int reg;
691 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
692
693 if (cmdlen < 4 || cmdbuf == NULL) {
694 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
695 cmdlen, (unsigned int)cmdbuf);
696 return -EINVAL;
697 }
698 /* Setup the indirect trigger address */
699 writel(plat->trigger_address,
700 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
701
702 /* Configure the opcode */
703 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
704 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
705
706 /* Setup write address. */
707 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
708 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
709
710 reg = readl(plat->regbase + CQSPI_REG_SIZE);
711 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
712 reg |= (addr_bytes - 1);
713 writel(reg, plat->regbase + CQSPI_REG_SIZE);
714 return 0;
715 }
716
cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata * plat,unsigned int n_tx,const u8 * txbuf)717 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
718 unsigned int n_tx, const u8 *txbuf)
719 {
720 unsigned int page_size = plat->page_size;
721 unsigned int remaining = n_tx;
722 unsigned int write_bytes;
723 int ret;
724
725 /* Configure the indirect read transfer bytes */
726 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
727
728 /* Start the indirect write transfer */
729 writel(CQSPI_REG_INDIRECTWR_START,
730 plat->regbase + CQSPI_REG_INDIRECTWR);
731
732 while (remaining > 0) {
733 write_bytes = remaining > page_size ? page_size : remaining;
734 /* Handle non-4-byte aligned access to avoid data abort. */
735 if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
736 writesb(plat->ahbbase, txbuf, write_bytes);
737 else
738 writesl(plat->ahbbase, txbuf, write_bytes >> 2);
739
740 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
741 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
742 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
743 if (ret) {
744 printf("Indirect write timed out (%i)\n", ret);
745 goto failwr;
746 }
747
748 txbuf += write_bytes;
749 remaining -= write_bytes;
750 }
751
752 /* Check indirect done status */
753 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
754 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
755 if (ret) {
756 printf("Indirect write completion error (%i)\n", ret);
757 goto failwr;
758 }
759
760 /* Clear indirect completion status */
761 writel(CQSPI_REG_INDIRECTWR_DONE,
762 plat->regbase + CQSPI_REG_INDIRECTWR);
763 return 0;
764
765 failwr:
766 /* Cancel the indirect write */
767 writel(CQSPI_REG_INDIRECTWR_CANCEL,
768 plat->regbase + CQSPI_REG_INDIRECTWR);
769 return ret;
770 }
771
cadence_qspi_apb_enter_xip(void * reg_base,char xip_dummy)772 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
773 {
774 unsigned int reg;
775
776 /* enter XiP mode immediately and enable direct mode */
777 reg = readl(reg_base + CQSPI_REG_CONFIG);
778 reg |= CQSPI_REG_CONFIG_ENABLE;
779 reg |= CQSPI_REG_CONFIG_DIRECT;
780 reg |= CQSPI_REG_CONFIG_XIP_IMM;
781 writel(reg, reg_base + CQSPI_REG_CONFIG);
782
783 /* keep the XiP mode */
784 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
785
786 /* Enable mode bit at devrd */
787 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
788 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
789 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
790 }
791