1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 3*4882a593Smuzhiyun * Altera Corporation <www.altera.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CADENCE_QSPI_H__ 9*4882a593Smuzhiyun #define __CADENCE_QSPI_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CQSPI_NO_DECODER_MAX_CS 4 14*4882a593Smuzhiyun #define CQSPI_DECODER_MAX_CS 16 15*4882a593Smuzhiyun #define CQSPI_READ_CAPTURE_MAX_DELAY 16 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct cadence_spi_platdata { 18*4882a593Smuzhiyun unsigned int max_hz; 19*4882a593Smuzhiyun void *regbase; 20*4882a593Smuzhiyun void *ahbbase; 21*4882a593Smuzhiyun bool is_decoded_cs; 22*4882a593Smuzhiyun u32 fifo_depth; 23*4882a593Smuzhiyun u32 fifo_width; 24*4882a593Smuzhiyun u32 trigger_address; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Flash parameters */ 27*4882a593Smuzhiyun u32 page_size; 28*4882a593Smuzhiyun u32 block_size; 29*4882a593Smuzhiyun u32 tshsl_ns; 30*4882a593Smuzhiyun u32 tsd2d_ns; 31*4882a593Smuzhiyun u32 tchsh_ns; 32*4882a593Smuzhiyun u32 tslch_ns; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct cadence_spi_priv { 36*4882a593Smuzhiyun void *regbase; 37*4882a593Smuzhiyun void *ahbbase; 38*4882a593Smuzhiyun size_t cmd_len; 39*4882a593Smuzhiyun u8 cmd_buf[32]; 40*4882a593Smuzhiyun size_t data_len; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun int qspi_is_init; 43*4882a593Smuzhiyun unsigned int qspi_calibrated_hz; 44*4882a593Smuzhiyun unsigned int qspi_calibrated_cs; 45*4882a593Smuzhiyun unsigned int previous_hz; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Functions call declaration */ 49*4882a593Smuzhiyun void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); 50*4882a593Smuzhiyun void cadence_qspi_apb_controller_enable(void *reg_base_addr); 51*4882a593Smuzhiyun void cadence_qspi_apb_controller_disable(void *reg_base_addr); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun int cadence_qspi_apb_command_read(void *reg_base_addr, 54*4882a593Smuzhiyun unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); 55*4882a593Smuzhiyun int cadence_qspi_apb_command_write(void *reg_base_addr, 56*4882a593Smuzhiyun unsigned int cmdlen, const u8 *cmdbuf, 57*4882a593Smuzhiyun unsigned int txlen, const u8 *txbuf); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, 60*4882a593Smuzhiyun unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); 61*4882a593Smuzhiyun int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, 62*4882a593Smuzhiyun unsigned int rxlen, u8 *rxbuf); 63*4882a593Smuzhiyun int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, 64*4882a593Smuzhiyun unsigned int cmdlen, const u8 *cmdbuf); 65*4882a593Smuzhiyun int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, 66*4882a593Smuzhiyun unsigned int txlen, const u8 *txbuf); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun void cadence_qspi_apb_chipselect(void *reg_base, 69*4882a593Smuzhiyun unsigned int chip_select, unsigned int decoder_enable); 70*4882a593Smuzhiyun void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); 71*4882a593Smuzhiyun void cadence_qspi_apb_config_baudrate_div(void *reg_base, 72*4882a593Smuzhiyun unsigned int ref_clk_hz, unsigned int sclk_hz); 73*4882a593Smuzhiyun void cadence_qspi_apb_delay(void *reg_base, 74*4882a593Smuzhiyun unsigned int ref_clk, unsigned int sclk_hz, 75*4882a593Smuzhiyun unsigned int tshsl_ns, unsigned int tsd2d_ns, 76*4882a593Smuzhiyun unsigned int tchsh_ns, unsigned int tslch_ns); 77*4882a593Smuzhiyun void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); 78*4882a593Smuzhiyun void cadence_qspi_apb_readdata_capture(void *reg_base, 79*4882a593Smuzhiyun unsigned int bypass, unsigned int delay); 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* __CADENCE_QSPI_H__ */ 82