1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Register definitions for the Atmel AT32/AT91 SPI Controller 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* Register offsets */ 6*4882a593Smuzhiyun #define ATMEL_SPI_CR 0x0000 7*4882a593Smuzhiyun #define ATMEL_SPI_MR 0x0004 8*4882a593Smuzhiyun #define ATMEL_SPI_RDR 0x0008 9*4882a593Smuzhiyun #define ATMEL_SPI_TDR 0x000c 10*4882a593Smuzhiyun #define ATMEL_SPI_SR 0x0010 11*4882a593Smuzhiyun #define ATMEL_SPI_IER 0x0014 12*4882a593Smuzhiyun #define ATMEL_SPI_IDR 0x0018 13*4882a593Smuzhiyun #define ATMEL_SPI_IMR 0x001c 14*4882a593Smuzhiyun #define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) 15*4882a593Smuzhiyun #define ATMEL_SPI_VERSION 0x00fc 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Bits in CR */ 18*4882a593Smuzhiyun #define ATMEL_SPI_CR_SPIEN BIT(0) 19*4882a593Smuzhiyun #define ATMEL_SPI_CR_SPIDIS BIT(1) 20*4882a593Smuzhiyun #define ATMEL_SPI_CR_SWRST BIT(7) 21*4882a593Smuzhiyun #define ATMEL_SPI_CR_LASTXFER BIT(24) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Bits in MR */ 24*4882a593Smuzhiyun #define ATMEL_SPI_MR_MSTR BIT(0) 25*4882a593Smuzhiyun #define ATMEL_SPI_MR_PS BIT(1) 26*4882a593Smuzhiyun #define ATMEL_SPI_MR_PCSDEC BIT(2) 27*4882a593Smuzhiyun #define ATMEL_SPI_MR_FDIV BIT(3) 28*4882a593Smuzhiyun #define ATMEL_SPI_MR_MODFDIS BIT(4) 29*4882a593Smuzhiyun #define ATMEL_SPI_MR_WDRBT BIT(5) 30*4882a593Smuzhiyun #define ATMEL_SPI_MR_LLB BIT(7) 31*4882a593Smuzhiyun #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) 32*4882a593Smuzhiyun #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Bits in RDR */ 35*4882a593Smuzhiyun #define ATMEL_SPI_RDR_RD(x) (x) 36*4882a593Smuzhiyun #define ATMEL_SPI_RDR_PCS(x) ((x) << 16) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Bits in TDR */ 39*4882a593Smuzhiyun #define ATMEL_SPI_TDR_TD(x) (x) 40*4882a593Smuzhiyun #define ATMEL_SPI_TDR_PCS(x) ((x) << 16) 41*4882a593Smuzhiyun #define ATMEL_SPI_TDR_LASTXFER BIT(24) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Bits in SR/IER/IDR/IMR */ 44*4882a593Smuzhiyun #define ATMEL_SPI_SR_RDRF BIT(0) 45*4882a593Smuzhiyun #define ATMEL_SPI_SR_TDRE BIT(1) 46*4882a593Smuzhiyun #define ATMEL_SPI_SR_MODF BIT(2) 47*4882a593Smuzhiyun #define ATMEL_SPI_SR_OVRES BIT(3) 48*4882a593Smuzhiyun #define ATMEL_SPI_SR_ENDRX BIT(4) 49*4882a593Smuzhiyun #define ATMEL_SPI_SR_ENDTX BIT(5) 50*4882a593Smuzhiyun #define ATMEL_SPI_SR_RXBUFF BIT(6) 51*4882a593Smuzhiyun #define ATMEL_SPI_SR_TXBUFE BIT(7) 52*4882a593Smuzhiyun #define ATMEL_SPI_SR_NSSR BIT(8) 53*4882a593Smuzhiyun #define ATMEL_SPI_SR_TXEMPTY BIT(9) 54*4882a593Smuzhiyun #define ATMEL_SPI_SR_SPIENS BIT(16) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Bits in CSRx */ 57*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_CPOL BIT(0) 58*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_NCPHA BIT(1) 59*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_CSAAT BIT(3) 60*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) 61*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) 62*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) 63*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) 64*4882a593Smuzhiyun #define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Bits in VERSION */ 67*4882a593Smuzhiyun #define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff) 68*4882a593Smuzhiyun #define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Constants for CSRx:BITS */ 71*4882a593Smuzhiyun #define ATMEL_SPI_BITS_8 0 72*4882a593Smuzhiyun #define ATMEL_SPI_BITS_9 1 73*4882a593Smuzhiyun #define ATMEL_SPI_BITS_10 2 74*4882a593Smuzhiyun #define ATMEL_SPI_BITS_11 3 75*4882a593Smuzhiyun #define ATMEL_SPI_BITS_12 4 76*4882a593Smuzhiyun #define ATMEL_SPI_BITS_13 5 77*4882a593Smuzhiyun #define ATMEL_SPI_BITS_14 6 78*4882a593Smuzhiyun #define ATMEL_SPI_BITS_15 7 79*4882a593Smuzhiyun #define ATMEL_SPI_BITS_16 8 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct atmel_spi_slave { 82*4882a593Smuzhiyun struct spi_slave slave; 83*4882a593Smuzhiyun void *regs; 84*4882a593Smuzhiyun u32 mr; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun to_atmel_spi(struct spi_slave * slave)87*4882a593Smuzhiyunstatic inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun return container_of(slave, struct atmel_spi_slave, slave); 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Register access macros */ 93*4882a593Smuzhiyun #define spi_readl(as, reg) \ 94*4882a593Smuzhiyun readl(as->regs + ATMEL_SPI_##reg) 95*4882a593Smuzhiyun #define spi_writel(as, reg, value) \ 96*4882a593Smuzhiyun writel(value, as->regs + ATMEL_SPI_##reg) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #if !defined(CONFIG_SYS_SPI_WRITE_TOUT) 99*4882a593Smuzhiyun #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 100*4882a593Smuzhiyun #endif 101