1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 Samsung Electronics 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __WM8994_REGISTERS_H__ 8*4882a593Smuzhiyun #define __WM8994_REGISTERS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * Register values. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define WM8994_SOFTWARE_RESET 0x00 14*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_1 0x01 15*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_2 0x02 16*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_4 0x04 17*4882a593Smuzhiyun #define WM8994_POWER_MANAGEMENT_5 0x05 18*4882a593Smuzhiyun #define WM8994_LEFT_OUTPUT_VOLUME 0x1C 19*4882a593Smuzhiyun #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 20*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_1 0x2D 21*4882a593Smuzhiyun #define WM8994_OUTPUT_MIXER_2 0x2E 22*4882a593Smuzhiyun #define WM8994_CHARGE_PUMP_1 0x4C 23*4882a593Smuzhiyun #define WM8994_DC_SERVO_1 0x54 24*4882a593Smuzhiyun #define WM8994_ANALOGUE_HP_1 0x60 25*4882a593Smuzhiyun #define WM8994_CHIP_REVISION 0x100 26*4882a593Smuzhiyun #define WM8994_AIF1_CLOCKING_1 0x200 27*4882a593Smuzhiyun #define WM8994_AIF1_CLOCKING_2 0x201 28*4882a593Smuzhiyun #define WM8994_AIF2_CLOCKING_1 0x204 29*4882a593Smuzhiyun #define WM8994_CLOCKING_1 0x208 30*4882a593Smuzhiyun #define WM8994_CLOCKING_2 0x209 31*4882a593Smuzhiyun #define WM8994_AIF1_RATE 0x210 32*4882a593Smuzhiyun #define WM8994_AIF2_RATE 0x211 33*4882a593Smuzhiyun #define WM8994_RATE_STATUS 0x212 34*4882a593Smuzhiyun #define WM8994_AIF1_CONTROL_1 0x300 35*4882a593Smuzhiyun #define WM8994_AIF1_CONTROL_2 0x301 36*4882a593Smuzhiyun #define WM8994_AIF1_MASTER_SLAVE 0x302 37*4882a593Smuzhiyun #define WM8994_AIF1_BCLK 0x303 38*4882a593Smuzhiyun #define WM8994_AIF2_CONTROL_1 0x310 39*4882a593Smuzhiyun #define WM8994_AIF2_CONTROL_2 0x311 40*4882a593Smuzhiyun #define WM8994_AIF2_MASTER_SLAVE 0x312 41*4882a593Smuzhiyun #define WM8994_AIF2_BCLK 0x313 42*4882a593Smuzhiyun #define WM8994_AIF1_DAC_FILTERS_1 0x420 43*4882a593Smuzhiyun #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 44*4882a593Smuzhiyun #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 45*4882a593Smuzhiyun #define WM8994_AIF2_DAC_FILTERS_1 0x520 46*4882a593Smuzhiyun #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 47*4882a593Smuzhiyun #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 48*4882a593Smuzhiyun #define WM8994_DAC1_LEFT_VOLUME 0x610 49*4882a593Smuzhiyun #define WM8994_DAC1_RIGHT_VOLUME 0x611 50*4882a593Smuzhiyun #define WM8994_GPIO_1 0x700 51*4882a593Smuzhiyun #define WM8994_GPIO_3 0x702 52*4882a593Smuzhiyun #define WM8994_GPIO_4 0x703 53*4882a593Smuzhiyun #define WM8994_GPIO_5 0x704 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Field Definitions. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * R0 (0x00) - Software Reset 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun /* SW_RESET */ 63*4882a593Smuzhiyun #define WM8994_SW_RESET 1 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun /* HPOUT1L_ENA */ 68*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA 0x0200 69*4882a593Smuzhiyun /* HPOUT1L_ENA */ 70*4882a593Smuzhiyun #define WM8994_HPOUT1L_ENA_MASK 0x0200 71*4882a593Smuzhiyun /* HPOUT1R_ENA */ 72*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA 0x0100 73*4882a593Smuzhiyun /* HPOUT1R_ENA */ 74*4882a593Smuzhiyun #define WM8994_HPOUT1R_ENA_MASK 0x0100 75*4882a593Smuzhiyun /* VMID_SEL - [2:1] */ 76*4882a593Smuzhiyun #define WM8994_VMID_SEL_MASK 0x0006 77*4882a593Smuzhiyun /* BIAS_ENA */ 78*4882a593Smuzhiyun #define WM8994_BIAS_ENA 0x0001 79*4882a593Smuzhiyun /* BIAS_ENA */ 80*4882a593Smuzhiyun #define WM8994_BIAS_ENA_MASK 0x0001 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun /* OPCLK_ENA */ 86*4882a593Smuzhiyun #define WM8994_OPCLK_ENA 0x0800 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define WM8994_TSHUT_ENA 0x4000 89*4882a593Smuzhiyun #define WM8994_MIXINL_ENA 0x0200 90*4882a593Smuzhiyun #define WM8994_MIXINR_ENA 0x0100 91*4882a593Smuzhiyun #define WM8994_IN2L_ENA 0x0080 92*4882a593Smuzhiyun #define WM8994_IN2R_ENA 0x0020 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * R5 (0x04) - Power Management (4) 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define WM8994_ADCL_ENA 0x0001 98*4882a593Smuzhiyun #define WM8994_ADCR_ENA 0x0002 99*4882a593Smuzhiyun #define WM8994_AIF1ADC1R_ENA 0x0100 100*4882a593Smuzhiyun #define WM8994_AIF1ADC1L_ENA 0x0200 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * R5 (0x05) - Power Management (5) 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun /* AIF2DACL_ENA */ 106*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA 0x2000 107*4882a593Smuzhiyun #define WM8994_AIF2DACL_ENA_MASK 0x2000 108*4882a593Smuzhiyun /* AIF2DACR_ENA */ 109*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA 0x1000 110*4882a593Smuzhiyun #define WM8994_AIF2DACR_ENA_MASK 0x1000 111*4882a593Smuzhiyun /* AIF1DACL_ENA */ 112*4882a593Smuzhiyun #define WM8994_AIF1DACL_ENA 0x0200 113*4882a593Smuzhiyun #define WM8994_AIF1DACL_ENA_MASK 0x0200 114*4882a593Smuzhiyun /* AIF1DACR_ENA */ 115*4882a593Smuzhiyun #define WM8994_AIF1DACR_ENA 0x0100 116*4882a593Smuzhiyun #define WM8994_AIF1DACR_ENA_MASK 0x0100 117*4882a593Smuzhiyun /* DAC1L_ENA */ 118*4882a593Smuzhiyun #define WM8994_DAC1L_ENA 0x0002 119*4882a593Smuzhiyun #define WM8994_DAC1L_ENA_MASK 0x0002 120*4882a593Smuzhiyun /* DAC1R_ENA */ 121*4882a593Smuzhiyun #define WM8994_DAC1R_ENA 0x0001 122*4882a593Smuzhiyun #define WM8994_DAC1R_ENA_MASK 0x0001 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * R45 (0x2D) - Output Mixer (1) 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun /* DAC1L_TO_HPOUT1L */ 128*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L 0x0100 129*4882a593Smuzhiyun #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * R46 (0x2E) - Output Mixer (2) 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun /* DAC1R_TO_HPOUT1R */ 135*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R 0x0100 136*4882a593Smuzhiyun #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * R76 (0x4C) - Charge Pump (1) 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun /* CP_ENA */ 142*4882a593Smuzhiyun #define WM8994_CP_ENA 0x8000 143*4882a593Smuzhiyun #define WM8994_CP_ENA_MASK 0x8000 144*4882a593Smuzhiyun /* 145*4882a593Smuzhiyun * R84 (0x54) - DC Servo (1) 146*4882a593Smuzhiyun */ 147*4882a593Smuzhiyun /* DCS_ENA_CHAN_1 */ 148*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1 0x0002 149*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 150*4882a593Smuzhiyun /* DCS_ENA_CHAN_0 */ 151*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0 0x0001 152*4882a593Smuzhiyun #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * R96 (0x60) - Analogue HP (1) 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun /* HPOUT1L_RMV_SHORT */ 158*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT 0x0080 159*4882a593Smuzhiyun #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 160*4882a593Smuzhiyun /* HPOUT1L_OUTP */ 161*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP 0x0040 162*4882a593Smuzhiyun #define WM8994_HPOUT1L_OUTP_MASK 0x0040 163*4882a593Smuzhiyun /* HPOUT1L_DLY */ 164*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY 0x0020 165*4882a593Smuzhiyun #define WM8994_HPOUT1L_DLY_MASK 0x0020 166*4882a593Smuzhiyun /* HPOUT1R_RMV_SHORT */ 167*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT 0x0008 168*4882a593Smuzhiyun #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 169*4882a593Smuzhiyun /* HPOUT1R_OUTP */ 170*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP 0x0004 171*4882a593Smuzhiyun #define WM8994_HPOUT1R_OUTP_MASK 0x0004 172*4882a593Smuzhiyun /* HPOUT1R_DLY */ 173*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY 0x0002 174*4882a593Smuzhiyun #define WM8994_HPOUT1R_DLY_MASK 0x0002 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * R512 (0x200) - AIF1 Clocking (1) 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun /* AIF1CLK_SRC - [4:3] */ 180*4882a593Smuzhiyun #define WM8994_AIF1CLK_SRC_MASK 0x0018 181*4882a593Smuzhiyun /* AIF1CLK_DIV */ 182*4882a593Smuzhiyun #define WM8994_AIF1CLK_DIV 0x0002 183*4882a593Smuzhiyun /* AIF1CLK_ENA */ 184*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA 0x0001 185*4882a593Smuzhiyun #define WM8994_AIF1CLK_ENA_MASK 0x0001 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* 188*4882a593Smuzhiyun * R517 (0x205) - AIF2 Clocking (2) 189*4882a593Smuzhiyun */ 190*4882a593Smuzhiyun /* AIF2DAC_DIV - [5:3] */ 191*4882a593Smuzhiyun #define WM8994_AIF2DAC_DIV_MASK 0x0038 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* 194*4882a593Smuzhiyun * R520 (0x208) - Clocking (1) 195*4882a593Smuzhiyun */ 196*4882a593Smuzhiyun /* AIF1DSPCLK_ENA */ 197*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA 0x0008 198*4882a593Smuzhiyun #define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 199*4882a593Smuzhiyun /* AIF2DSPCLK_ENA */ 200*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA 0x0004 201*4882a593Smuzhiyun #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 202*4882a593Smuzhiyun /* SYSDSPCLK_ENA */ 203*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA 0x0002 204*4882a593Smuzhiyun #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 205*4882a593Smuzhiyun /* SYSCLK_SRC */ 206*4882a593Smuzhiyun #define WM8994_SYSCLK_SRC 0x0001 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* 209*4882a593Smuzhiyun * R521 (0x209) - Clocking (2) 210*4882a593Smuzhiyun */ 211*4882a593Smuzhiyun /* OPCLK_DIV - [2:0] */ 212*4882a593Smuzhiyun #define WM8994_OPCLK_DIV_MASK 0x0007 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* 215*4882a593Smuzhiyun * R528 (0x210) - AIF1 Rate 216*4882a593Smuzhiyun */ 217*4882a593Smuzhiyun /* AIF1_SR - [7:4] */ 218*4882a593Smuzhiyun #define WM8994_AIF1_SR_MASK 0x00F0 219*4882a593Smuzhiyun #define WM8994_AIF1_SR_SHIFT 4 220*4882a593Smuzhiyun /* AIF1CLK_RATE - [3:0] */ 221*4882a593Smuzhiyun #define WM8994_AIF1CLK_RATE_MASK 0x000F 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* 224*4882a593Smuzhiyun * R768 (0x300) - AIF1 Control (1) 225*4882a593Smuzhiyun */ 226*4882a593Smuzhiyun /* AIF1_BCLK_INV */ 227*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_INV 0x0100 228*4882a593Smuzhiyun /* AIF1_LRCLK_INV */ 229*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV 0x0080 230*4882a593Smuzhiyun #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 231*4882a593Smuzhiyun /* AIF1_WL - [6:5] */ 232*4882a593Smuzhiyun #define WM8994_AIF1_WL_MASK 0x0060 233*4882a593Smuzhiyun /* AIF1_FMT - [4:3] */ 234*4882a593Smuzhiyun #define WM8994_AIF1_FMT_MASK 0x0018 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* 237*4882a593Smuzhiyun * R769 (0x301) - AIF1 Control (2) 238*4882a593Smuzhiyun */ 239*4882a593Smuzhiyun /* AIF1_MONO */ 240*4882a593Smuzhiyun #define WM8994_AIF1_MONO 0x0100 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun /* 243*4882a593Smuzhiyun * R770 (0x302) - AIF1 Master/Slave 244*4882a593Smuzhiyun */ 245*4882a593Smuzhiyun /* AIF1_MSTR */ 246*4882a593Smuzhiyun #define WM8994_AIF1_MSTR 0x4000 247*4882a593Smuzhiyun #define WM8994_AIF1_MSTR_MASK 0x4000 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* 250*4882a593Smuzhiyun * R771 (0x303) - AIF1 BCLK 251*4882a593Smuzhiyun */ 252*4882a593Smuzhiyun /* AIF1_BCLK_DIV - [8:4] */ 253*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 254*4882a593Smuzhiyun #define WM8994_AIF1_BCLK_DIV_SHIFT 4 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* 257*4882a593Smuzhiyun * R1282 (0x502) - AIF2 DAC Left Volume 258*4882a593Smuzhiyun */ 259*4882a593Smuzhiyun /* AIF2DAC_VU */ 260*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU 0x0100 261*4882a593Smuzhiyun #define WM8994_AIF2DAC_VU_MASK 0x0100 262*4882a593Smuzhiyun /* AIF2DACL_VOL - [7:0] */ 263*4882a593Smuzhiyun #define WM8994_AIF2DACL_VOL_MASK 0x00FF 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun /* 266*4882a593Smuzhiyun * R1283 (0x503) - AIF2 DAC Right Volume 267*4882a593Smuzhiyun */ 268*4882a593Smuzhiyun /* AIF2DACR_VOL - [7:0] */ 269*4882a593Smuzhiyun #define WM8994_AIF2DACR_VOL_MASK 0x00FF 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun /* 272*4882a593Smuzhiyun * R1312 (0x520) - AIF2 DAC Filters (1) 273*4882a593Smuzhiyun */ 274*4882a593Smuzhiyun /* AIF2DAC_MUTE */ 275*4882a593Smuzhiyun #define WM8994_AIF2DAC_MUTE_MASK 0x0200 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* 278*4882a593Smuzhiyun * R1537 (0x601) - DAC1 Left Mixer Routing 279*4882a593Smuzhiyun */ 280*4882a593Smuzhiyun /* AIF2DACL_TO_DAC1L */ 281*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L 0x0004 282*4882a593Smuzhiyun #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 283*4882a593Smuzhiyun /* AIF1DAC1L_TO_DAC1L */ 284*4882a593Smuzhiyun #define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* 287*4882a593Smuzhiyun * R1538 (0x602) - DAC1 Right Mixer Routing 288*4882a593Smuzhiyun */ 289*4882a593Smuzhiyun /* AIF2DACR_TO_DAC1R */ 290*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R 0x0004 291*4882a593Smuzhiyun #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 292*4882a593Smuzhiyun /* AIF1DAC1R_TO_DAC1R */ 293*4882a593Smuzhiyun #define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* 296*4882a593Smuzhiyun * R1552 (0x610) - DAC1 Left Volume 297*4882a593Smuzhiyun */ 298*4882a593Smuzhiyun /* DAC1L_MUTE */ 299*4882a593Smuzhiyun #define WM8994_DAC1L_MUTE_MASK 0x0200 300*4882a593Smuzhiyun /* DAC1_VU */ 301*4882a593Smuzhiyun #define WM8994_DAC1_VU 0x0100 302*4882a593Smuzhiyun #define WM8994_DAC1_VU_MASK 0x0100 303*4882a593Smuzhiyun /* DAC1L_VOL - [7:0] */ 304*4882a593Smuzhiyun #define WM8994_DAC1L_VOL_MASK 0x00FF 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun /* 307*4882a593Smuzhiyun * R1553 (0x611) - DAC1 Right Volume 308*4882a593Smuzhiyun */ 309*4882a593Smuzhiyun /* DAC1R_MUTE */ 310*4882a593Smuzhiyun #define WM8994_DAC1R_MUTE_MASK 0x0200 311*4882a593Smuzhiyun /* DAC1R_VOL - [7:0] */ 312*4882a593Smuzhiyun #define WM8994_DAC1R_VOL_MASK 0x00FF 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* 315*4882a593Smuzhiyun * GPIO 316*4882a593Smuzhiyun */ 317*4882a593Smuzhiyun /* OUTPUT PIN */ 318*4882a593Smuzhiyun #define WM8994_GPIO_DIR_OUTPUT 0x8000 319*4882a593Smuzhiyun /* GPIO PIN MASK */ 320*4882a593Smuzhiyun #define WM8994_GPIO_DIR_MASK 0xFFE0 321*4882a593Smuzhiyun /* I2S CLK */ 322*4882a593Smuzhiyun #define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001 323*4882a593Smuzhiyun #define WM8994_GPIO_INPUT_DEBOUNCE 0x0100 324*4882a593Smuzhiyun /* GPn FN */ 325*4882a593Smuzhiyun #define WM8994_GPIO_FUNCTION_MASK 0x001F 326*4882a593Smuzhiyun #endif 327