1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * R. Chadrasekar <rcsekar@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __WM8994_H__ 9*4882a593Smuzhiyun #define __WM8994_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 12*4882a593Smuzhiyun #define WM8994_SYSCLK_MCLK1 1 13*4882a593Smuzhiyun #define WM8994_SYSCLK_MCLK2 2 14*4882a593Smuzhiyun #define WM8994_SYSCLK_FLL1 3 15*4882a593Smuzhiyun #define WM8994_SYSCLK_FLL2 4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Avilable audi interface ports in wm8994 codec */ 18*4882a593Smuzhiyun enum en_audio_interface { 19*4882a593Smuzhiyun WM8994_AIF1 = 1, 20*4882a593Smuzhiyun WM8994_AIF2, 21*4882a593Smuzhiyun WM8994_AIF3 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */ 25*4882a593Smuzhiyun #define WM8994_SYSCLK_OPCLK 5 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define WM8994_FLL1 1 28*4882a593Smuzhiyun #define WM8994_FLL2 2 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define WM8994_FLL_SRC_MCLK1 1 31*4882a593Smuzhiyun #define WM8994_FLL_SRC_MCLK2 2 32*4882a593Smuzhiyun #define WM8994_FLL_SRC_LRCLK 3 33*4882a593Smuzhiyun #define WM8994_FLL_SRC_BCLK 4 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* maximum available digital interfac in the dac to configure */ 36*4882a593Smuzhiyun #define WM8994_MAX_AIF 2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define WM8994_MAX_INPUT_CLK_FREQ 13500000 39*4882a593Smuzhiyun #define WM8994_ID 0x8994 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum wm8994_vmid_mode { 42*4882a593Smuzhiyun WM8994_VMID_NORMAL, 43*4882a593Smuzhiyun WM8994_VMID_FORCE, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* wm 8994 family devices */ 47*4882a593Smuzhiyun enum wm8994_type { 48*4882a593Smuzhiyun WM8994 = 0, 49*4882a593Smuzhiyun WM8958 = 1, 50*4882a593Smuzhiyun WM1811 = 2, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * intialise wm8994 sound codec device for the given configuration 55*4882a593Smuzhiyun * 56*4882a593Smuzhiyun * @param blob FDT node for codec values 57*4882a593Smuzhiyun * @param aif_id enum value of codec interface port in which 58*4882a593Smuzhiyun * soc i2s is connected 59*4882a593Smuzhiyun * @param sampling_rate Sampling rate ranges between from 8khz to 96khz 60*4882a593Smuzhiyun * @param mclk_freq Master clock frequency. 61*4882a593Smuzhiyun * @param bits_per_sample bits per Sample can be 16 or 24 62*4882a593Smuzhiyun * @param channels Number of channnels, maximum 2 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * @returns -1 for error and 0 Success. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun int wm8994_init(const void *blob, enum en_audio_interface aif_id, 67*4882a593Smuzhiyun int sampling_rate, int mclk_freq, 68*4882a593Smuzhiyun int bits_per_sample, unsigned int channels); 69*4882a593Smuzhiyun #endif /*__WM8994_H__ */ 70