1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ROCKCHIP_I2S_H__ 7*4882a593Smuzhiyun #define __ROCKCHIP_I2S_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* I2S REGS */ 10*4882a593Smuzhiyun #define I2S_TXCR (0x0000) 11*4882a593Smuzhiyun #define I2S_RXCR (0x0004) 12*4882a593Smuzhiyun #define I2S_CKR (0x0008) 13*4882a593Smuzhiyun #define I2S_FIFOLR (0x000c) 14*4882a593Smuzhiyun #define I2S_DMACR (0x0010) 15*4882a593Smuzhiyun #define I2S_INTCR (0x0014) 16*4882a593Smuzhiyun #define I2S_INTSR (0x0018) 17*4882a593Smuzhiyun #define I2S_XFER (0x001c) 18*4882a593Smuzhiyun #define I2S_CLR (0x0020) 19*4882a593Smuzhiyun #define I2S_TXDR (0x0024) 20*4882a593Smuzhiyun #define I2S_RXDR (0x0028) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * TXCR 24*4882a593Smuzhiyun * transmit operation control register 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define I2S_TXCR_RCNT_SHIFT 17 27*4882a593Smuzhiyun #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 28*4882a593Smuzhiyun #define I2S_TXCR_CSR_SHIFT 15 29*4882a593Smuzhiyun #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) 30*4882a593Smuzhiyun #define I2S_TXCR_CHN_2 (0 << I2S_TXCR_CSR_SHIFT) 31*4882a593Smuzhiyun #define I2S_TXCR_CHN_4 (1 << I2S_TXCR_CSR_SHIFT) 32*4882a593Smuzhiyun #define I2S_TXCR_CHN_6 (2 << I2S_TXCR_CSR_SHIFT) 33*4882a593Smuzhiyun #define I2S_TXCR_CHN_8 (3 << I2S_TXCR_CSR_SHIFT) 34*4882a593Smuzhiyun #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 35*4882a593Smuzhiyun #define I2S_TXCR_HWT BIT(14) 36*4882a593Smuzhiyun #define I2S_TXCR_SJM_SHIFT 12 37*4882a593Smuzhiyun #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 38*4882a593Smuzhiyun #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 39*4882a593Smuzhiyun #define I2S_TXCR_FBM_SHIFT 11 40*4882a593Smuzhiyun #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 41*4882a593Smuzhiyun #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 42*4882a593Smuzhiyun #define I2S_TXCR_IBM_SHIFT 9 43*4882a593Smuzhiyun #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 44*4882a593Smuzhiyun #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 45*4882a593Smuzhiyun #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 46*4882a593Smuzhiyun #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 47*4882a593Smuzhiyun #define I2S_TXCR_PBM_SHIFT 7 48*4882a593Smuzhiyun #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) 49*4882a593Smuzhiyun #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 50*4882a593Smuzhiyun #define I2S_TXCR_TFS_SHIFT 5 51*4882a593Smuzhiyun #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 52*4882a593Smuzhiyun #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 53*4882a593Smuzhiyun #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT) 54*4882a593Smuzhiyun #define I2S_TXCR_VDW_SHIFT 0 55*4882a593Smuzhiyun #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) 56*4882a593Smuzhiyun #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * RXCR 60*4882a593Smuzhiyun * receive operation control register 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define I2S_RXCR_CSR_SHIFT 15 63*4882a593Smuzhiyun #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) 64*4882a593Smuzhiyun #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 65*4882a593Smuzhiyun #define I2S_RXCR_HWT BIT(14) 66*4882a593Smuzhiyun #define I2S_RXCR_SJM_SHIFT 12 67*4882a593Smuzhiyun #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 68*4882a593Smuzhiyun #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 69*4882a593Smuzhiyun #define I2S_RXCR_FBM_SHIFT 11 70*4882a593Smuzhiyun #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 71*4882a593Smuzhiyun #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 72*4882a593Smuzhiyun #define I2S_RXCR_IBM_SHIFT 9 73*4882a593Smuzhiyun #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 74*4882a593Smuzhiyun #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 75*4882a593Smuzhiyun #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 76*4882a593Smuzhiyun #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 77*4882a593Smuzhiyun #define I2S_RXCR_PBM_SHIFT 7 78*4882a593Smuzhiyun #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) 79*4882a593Smuzhiyun #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 80*4882a593Smuzhiyun #define I2S_RXCR_TFS_SHIFT 5 81*4882a593Smuzhiyun #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 82*4882a593Smuzhiyun #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 83*4882a593Smuzhiyun #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT) 84*4882a593Smuzhiyun #define I2S_RXCR_VDW_SHIFT 0 85*4882a593Smuzhiyun #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) 86*4882a593Smuzhiyun #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * CKR 90*4882a593Smuzhiyun * clock generation register 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define I2S_CKR_MSS_SHIFT 27 93*4882a593Smuzhiyun #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 94*4882a593Smuzhiyun #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 95*4882a593Smuzhiyun #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 96*4882a593Smuzhiyun #define I2S_CKR_CKP_SHIFT 26 97*4882a593Smuzhiyun #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) 98*4882a593Smuzhiyun #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) 99*4882a593Smuzhiyun #define I2S_CKR_RLP_SHIFT 25 100*4882a593Smuzhiyun #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 101*4882a593Smuzhiyun #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) 102*4882a593Smuzhiyun #define I2S_CKR_TLP_SHIFT 24 103*4882a593Smuzhiyun #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 104*4882a593Smuzhiyun #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT) 105*4882a593Smuzhiyun #define I2S_CKR_MDIV_SHIFT 16 106*4882a593Smuzhiyun #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) 107*4882a593Smuzhiyun #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 108*4882a593Smuzhiyun #define I2S_CKR_RSD_SHIFT 8 109*4882a593Smuzhiyun #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) 110*4882a593Smuzhiyun #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 111*4882a593Smuzhiyun #define I2S_CKR_TSD_SHIFT 0 112*4882a593Smuzhiyun #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) 113*4882a593Smuzhiyun #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* 116*4882a593Smuzhiyun * FIFOLR 117*4882a593Smuzhiyun * FIFO level register 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define I2S_FIFOLR_RFL_SHIFT 24 120*4882a593Smuzhiyun #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) 121*4882a593Smuzhiyun #define I2S_FIFOLR_TFL3_SHIFT 18 122*4882a593Smuzhiyun #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) 123*4882a593Smuzhiyun #define I2S_FIFOLR_TFL2_SHIFT 12 124*4882a593Smuzhiyun #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) 125*4882a593Smuzhiyun #define I2S_FIFOLR_TFL1_SHIFT 6 126*4882a593Smuzhiyun #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) 127*4882a593Smuzhiyun #define I2S_FIFOLR_TFL0_SHIFT 0 128*4882a593Smuzhiyun #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * DMACR 132*4882a593Smuzhiyun * DMA control register 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun #define I2S_DMACR_RDE_SHIFT 24 135*4882a593Smuzhiyun #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 136*4882a593Smuzhiyun #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 137*4882a593Smuzhiyun #define I2S_DMACR_RDE_MASK (1 << I2S_DMACR_RDE_SHIFT) 138*4882a593Smuzhiyun #define I2S_DMACR_RDL_SHIFT 16 139*4882a593Smuzhiyun #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) 140*4882a593Smuzhiyun #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 141*4882a593Smuzhiyun #define I2S_DMACR_TDE_SHIFT 8 142*4882a593Smuzhiyun #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 143*4882a593Smuzhiyun #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 144*4882a593Smuzhiyun #define I2S_DMACR_TDE_MASK (1 << I2S_DMACR_TDE_SHIFT) 145*4882a593Smuzhiyun #define I2S_DMACR_TDL_SHIFT 0 146*4882a593Smuzhiyun #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 147*4882a593Smuzhiyun #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * INTCR 151*4882a593Smuzhiyun * interrupt control register 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun #define I2S_INTCR_RFT_SHIFT 20 154*4882a593Smuzhiyun #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) 155*4882a593Smuzhiyun #define I2S_INTCR_RXOIC BIT(18) 156*4882a593Smuzhiyun #define I2S_INTCR_RXOIE_SHIFT 17 157*4882a593Smuzhiyun #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) 158*4882a593Smuzhiyun #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) 159*4882a593Smuzhiyun #define I2S_INTCR_RXFIE_SHIFT 16 160*4882a593Smuzhiyun #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) 161*4882a593Smuzhiyun #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) 162*4882a593Smuzhiyun #define I2S_INTCR_TFT_SHIFT 4 163*4882a593Smuzhiyun #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) 164*4882a593Smuzhiyun #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) 165*4882a593Smuzhiyun #define I2S_INTCR_TXUIC BIT(2) 166*4882a593Smuzhiyun #define I2S_INTCR_TXUIE_SHIFT 1 167*4882a593Smuzhiyun #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) 168*4882a593Smuzhiyun #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * INTSR 172*4882a593Smuzhiyun * interrupt status register 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define I2S_INTSR_RXOI_SHIFT 17 175*4882a593Smuzhiyun #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) 176*4882a593Smuzhiyun #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) 177*4882a593Smuzhiyun #define I2S_INTSR_RXFI_SHIFT 16 178*4882a593Smuzhiyun #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) 179*4882a593Smuzhiyun #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) 180*4882a593Smuzhiyun #define I2S_INTSR_TXUI_SHIFT 1 181*4882a593Smuzhiyun #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) 182*4882a593Smuzhiyun #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) 183*4882a593Smuzhiyun #define I2S_INTSR_TXEI_SHIFT 0 184*4882a593Smuzhiyun #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) 185*4882a593Smuzhiyun #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* 188*4882a593Smuzhiyun * XFER 189*4882a593Smuzhiyun * Transfer start register 190*4882a593Smuzhiyun */ 191*4882a593Smuzhiyun #define I2S_XFER_RXS_SHIFT 1 192*4882a593Smuzhiyun #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 193*4882a593Smuzhiyun #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 194*4882a593Smuzhiyun #define I2S_XFER_RXS_MASK (1 << I2S_XFER_RXS_SHIFT) 195*4882a593Smuzhiyun #define I2S_XFER_TXS_SHIFT 0 196*4882a593Smuzhiyun #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 197*4882a593Smuzhiyun #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 198*4882a593Smuzhiyun #define I2S_XFER_TXS_MASK (1 << I2S_XFER_TXS_SHIFT) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * CLR 202*4882a593Smuzhiyun * clear SCLK domain logic register 203*4882a593Smuzhiyun */ 204*4882a593Smuzhiyun #define I2S_CLR_RXC BIT(1) 205*4882a593Smuzhiyun #define I2S_CLR_RXC_MASK BIT(1) 206*4882a593Smuzhiyun #define I2S_CLR_TXC BIT(0) 207*4882a593Smuzhiyun #define I2S_CLR_TXC_MASK BIT(0) 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #endif 210