1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __RK817_CODEC_H__ 7*4882a593Smuzhiyun #define __RK817_CODEC_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* codec register */ 10*4882a593Smuzhiyun #define RK817_CODEC_BASE 0x0000 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12) 13*4882a593Smuzhiyun #define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13) 14*4882a593Smuzhiyun #define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14) 15*4882a593Smuzhiyun #define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15) 16*4882a593Smuzhiyun #define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16) 17*4882a593Smuzhiyun #define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17) 18*4882a593Smuzhiyun #define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18) 19*4882a593Smuzhiyun #define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19) 20*4882a593Smuzhiyun #define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a) 21*4882a593Smuzhiyun #define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b) 22*4882a593Smuzhiyun #define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e) 23*4882a593Smuzhiyun #define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f) 24*4882a593Smuzhiyun #define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20) 25*4882a593Smuzhiyun #define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21) 26*4882a593Smuzhiyun #define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22) 27*4882a593Smuzhiyun #define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23) 28*4882a593Smuzhiyun #define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24) 29*4882a593Smuzhiyun #define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27) 30*4882a593Smuzhiyun #define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28) 31*4882a593Smuzhiyun #define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29) 32*4882a593Smuzhiyun #define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a) 33*4882a593Smuzhiyun #define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b) 34*4882a593Smuzhiyun #define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c) 35*4882a593Smuzhiyun #define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d) 36*4882a593Smuzhiyun #define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e) 37*4882a593Smuzhiyun #define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f) 38*4882a593Smuzhiyun #define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30) 39*4882a593Smuzhiyun #define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31) 40*4882a593Smuzhiyun #define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32) 41*4882a593Smuzhiyun #define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35) 42*4882a593Smuzhiyun #define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36) 43*4882a593Smuzhiyun #define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37) 44*4882a593Smuzhiyun #define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38) 45*4882a593Smuzhiyun #define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39) 46*4882a593Smuzhiyun #define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a) 47*4882a593Smuzhiyun #define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b) 48*4882a593Smuzhiyun #define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c) 49*4882a593Smuzhiyun #define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d) 50*4882a593Smuzhiyun #define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e) 51*4882a593Smuzhiyun #define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f) 52*4882a593Smuzhiyun #define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40) 53*4882a593Smuzhiyun #define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41) 54*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42) 55*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43) 56*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44) 57*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45) 58*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46) 59*4882a593Smuzhiyun #define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47) 60*4882a593Smuzhiyun #define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48) 61*4882a593Smuzhiyun #define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49) 62*4882a593Smuzhiyun #define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a) 63*4882a593Smuzhiyun #define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b) 64*4882a593Smuzhiyun #define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c) 65*4882a593Smuzhiyun #define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d) 66*4882a593Smuzhiyun #define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e) 67*4882a593Smuzhiyun #define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* RK817_CODEC_DTOP_DIGEN_CLKE */ 70*4882a593Smuzhiyun #define ADC_DIG_CLK_MASK (0xf << 4) 71*4882a593Smuzhiyun #define ADC_DIG_CLK_SFT 4 72*4882a593Smuzhiyun #define ADC_DIG_CLK_DIS (0x0 << 4) 73*4882a593Smuzhiyun #define ADC_DIG_CLK_EN (0xf << 4) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define DAC_DIG_CLK_MASK (0xf << 0) 76*4882a593Smuzhiyun #define DAC_DIG_CLK_SFT 0 77*4882a593Smuzhiyun #define DAC_DIG_CLK_DIS (0x0 << 0) 78*4882a593Smuzhiyun #define DAC_DIG_CLK_EN (0xf << 0) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* RK817_CODEC_APLL_CFG5 */ 81*4882a593Smuzhiyun #define PLL_PW_DOWN (0x01 << 0) 82*4882a593Smuzhiyun #define PLL_PW_UP (0x00 << 0) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* RK817_CODEC_DI2S_CKM */ 85*4882a593Smuzhiyun #define PDM_EN_MASK (0x1 << 3) 86*4882a593Smuzhiyun #define PDM_EN_SFT 3 87*4882a593Smuzhiyun #define PDM_EN_DISABLE (0x0 << 3) 88*4882a593Smuzhiyun #define PDM_EN_ENABLE (0x1 << 3) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define SCK_EN_ENABLE (0x1 << 2) 91*4882a593Smuzhiyun #define SCK_EN_DISABLE (0x0 << 2) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RK817_I2S_MODE_MASK (0x1 << 0) 94*4882a593Smuzhiyun #define RK817_I2S_MODE_SFT 0 95*4882a593Smuzhiyun #define RK817_I2S_MODE_MST (0x1 << 0) 96*4882a593Smuzhiyun #define RK817_I2S_MODE_SLV (0x0 << 0) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* RK817_CODEC_DDAC_MUTE_MIXCTL */ 99*4882a593Smuzhiyun #define DACMT_ENABLE (0x1 << 0) 100*4882a593Smuzhiyun #define DACMT_DISABLE (0x0 << 0) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* RK817_CODEC_DI2S_RXCR2 */ 103*4882a593Smuzhiyun #define VDW_RX_24BITS (0x17) 104*4882a593Smuzhiyun #define VDW_RX_16BITS (0x0f) 105*4882a593Smuzhiyun /* RK817_CODEC_DI2S_TXCR2 */ 106*4882a593Smuzhiyun #define VDW_TX_24BITS (0x17) 107*4882a593Smuzhiyun #define VDW_TX_16BITS (0x0f) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* RK817_CODEC_AHP_CFG1 */ 110*4882a593Smuzhiyun #define HP_ANTIPOP_ENABLE (0x1 << 4) 111*4882a593Smuzhiyun #define HP_ANTIPOP_DISABLE (0x0 << 4) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* RK817_CODEC_ADAC_CFG1 */ 114*4882a593Smuzhiyun #define PWD_DACBIAS_MASK (0x1 << 3) 115*4882a593Smuzhiyun #define PWD_DACBIAS_SFT 3 116*4882a593Smuzhiyun #define PWD_DACBIAS_DOWN (0x1 << 3) 117*4882a593Smuzhiyun #define PWD_DACBIAS_ON (0x0 << 3) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define PWD_DACD_MASK (0x1 << 2) 120*4882a593Smuzhiyun #define PWD_DACD_SFT 2 121*4882a593Smuzhiyun #define PWD_DACD_DOWN (0x1 << 2) 122*4882a593Smuzhiyun #define PWD_DACD_ON (0x0 << 2) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define PWD_DACL_MASK (0x1 << 1) 125*4882a593Smuzhiyun #define PWD_DACL_SFT 1 126*4882a593Smuzhiyun #define PWD_DACL_DOWN (0x1 << 1) 127*4882a593Smuzhiyun #define PWD_DACL_ON (0x0 << 1) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define PWD_DACR_MASK (0x1 << 0) 130*4882a593Smuzhiyun #define PWD_DACR_SFT 0 131*4882a593Smuzhiyun #define PWD_DACR_DOWN (0x1 << 0) 132*4882a593Smuzhiyun #define PWD_DACR_ON (0x0 << 0) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* RK817_CODEC_AADC_CFG0 */ 135*4882a593Smuzhiyun #define ADC_L_PWD_MASK (0x1 << 7) 136*4882a593Smuzhiyun #define ADC_L_PWD_SFT 7 137*4882a593Smuzhiyun #define ADC_L_PWD_DIS (0x0 << 7) 138*4882a593Smuzhiyun #define ADC_L_PWD_EN (0x1 << 7) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define ADC_R_PWD_MASK (0x1 << 6) 141*4882a593Smuzhiyun #define ADC_R_PWD_SFT 6 142*4882a593Smuzhiyun #define ADC_R_PWD_DIS (0x0 << 6) 143*4882a593Smuzhiyun #define ADC_R_PWD_EN (0x1 << 6) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* RK817_CODEC_AMIC_CFG0 */ 146*4882a593Smuzhiyun #define MIC_DIFF_MASK (0x1 << 7) 147*4882a593Smuzhiyun #define MIC_DIFF_SFT 7 148*4882a593Smuzhiyun #define MIC_DIFF_DIS (0x0 << 7) 149*4882a593Smuzhiyun #define MIC_DIFF_EN (0x1 << 7) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define PWD_PGA_L_MASK (0x1 << 5) 152*4882a593Smuzhiyun #define PWD_PGA_L_SFT 5 153*4882a593Smuzhiyun #define PWD_PGA_L_DIS (0x0 << 5) 154*4882a593Smuzhiyun #define PWD_PGA_L_EN (0x1 << 5) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define PWD_PGA_R_MASK (0x1 << 4) 157*4882a593Smuzhiyun #define PWD_PGA_R_SFT 4 158*4882a593Smuzhiyun #define PWD_PGA_R_DIS (0x0 << 4) 159*4882a593Smuzhiyun #define PWD_PGA_R_EN (0x1 << 4) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun enum { 162*4882a593Smuzhiyun RK817_HIFI, 163*4882a593Smuzhiyun RK817_VOICE, 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun enum { 167*4882a593Smuzhiyun RK817_MONO = 1, 168*4882a593Smuzhiyun RK817_STEREO, 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun enum { 172*4882a593Smuzhiyun OFF, 173*4882a593Smuzhiyun RCV, 174*4882a593Smuzhiyun SPK_PATH, 175*4882a593Smuzhiyun HP_PATH, 176*4882a593Smuzhiyun HP_NO_MIC, 177*4882a593Smuzhiyun BT, 178*4882a593Smuzhiyun SPK_HP, 179*4882a593Smuzhiyun RING_SPK, 180*4882a593Smuzhiyun RING_HP, 181*4882a593Smuzhiyun RING_HP_NO_MIC, 182*4882a593Smuzhiyun RING_SPK_HP, 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun enum { 186*4882a593Smuzhiyun MIC_OFF, 187*4882a593Smuzhiyun MAIN_MIC, 188*4882a593Smuzhiyun HANDS_FREE_MIC, 189*4882a593Smuzhiyun BT_SCO_MIC, 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun struct rk817_reg_val_typ { 193*4882a593Smuzhiyun unsigned int reg; 194*4882a593Smuzhiyun unsigned int value; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun struct rk817_init_bit_typ { 198*4882a593Smuzhiyun unsigned int reg; 199*4882a593Smuzhiyun unsigned int power_bit; 200*4882a593Smuzhiyun unsigned int init_bit; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #endif /* __RK817_CODEC_H__ */ 204