1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 3*4882a593Smuzhiyun * Vikas Manocha, <vikas.manocha@st.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SERIAL_STM32_X7_ 9*4882a593Smuzhiyun #define _SERIAL_STM32_X7_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct stm32_usart { 12*4882a593Smuzhiyun u32 cr1; 13*4882a593Smuzhiyun u32 cr2; 14*4882a593Smuzhiyun u32 cr3; 15*4882a593Smuzhiyun u32 brr; 16*4882a593Smuzhiyun u32 gtpr; 17*4882a593Smuzhiyun u32 rtor; 18*4882a593Smuzhiyun u32 rqr; 19*4882a593Smuzhiyun u32 sr; 20*4882a593Smuzhiyun u32 icr; 21*4882a593Smuzhiyun u32 rd_dr; 22*4882a593Smuzhiyun u32 tx_dr; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Information about a serial port */ 26*4882a593Smuzhiyun struct stm32x7_serial_platdata { 27*4882a593Smuzhiyun struct stm32_usart *base; /* address of registers in physical memory */ 28*4882a593Smuzhiyun unsigned long int clock_rate; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define USART_CR1_OVER8 (1 << 15) 32*4882a593Smuzhiyun #define USART_CR1_TE (1 << 3) 33*4882a593Smuzhiyun #define USART_CR1_RE (1 << 2) 34*4882a593Smuzhiyun #define USART_CR1_UE (1 << 0) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define USART_CR3_OVRDIS (1 << 12) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define USART_SR_FLAG_RXNE (1 << 5) 39*4882a593Smuzhiyun #define USART_SR_FLAG_TXE (1 << 7) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define USART_BRR_F_MASK 0xFF 42*4882a593Smuzhiyun #define USART_BRR_M_SHIFT 4 43*4882a593Smuzhiyun #define USART_BRR_M_MASK 0xFFF0 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46