xref: /OK3568_Linux_fs/u-boot/drivers/serial/serial_sti_asc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Support for Serial I/O using STMicroelectronics' on-chip ASC.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (c) 2017
5*4882a593Smuzhiyun  *  Patrice Chotard <patrice.chotard@st.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <serial.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define BAUDMODE	0x00001000
18*4882a593Smuzhiyun #define RXENABLE	0x00000100
19*4882a593Smuzhiyun #define RUN		0x00000080
20*4882a593Smuzhiyun #define MODE		0x00000001
21*4882a593Smuzhiyun #define MODE_8BIT	0x0001
22*4882a593Smuzhiyun #define STOP_1BIT	0x0008
23*4882a593Smuzhiyun #define PARITYODD	0x0020
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define STA_TF		BIT(9)
26*4882a593Smuzhiyun #define STA_RBF		BIT(0)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct sti_asc_uart {
29*4882a593Smuzhiyun 	u32 baudrate;
30*4882a593Smuzhiyun 	u32 txbuf;
31*4882a593Smuzhiyun 	u32 rxbuf;
32*4882a593Smuzhiyun 	u32 control;
33*4882a593Smuzhiyun 	u32 inten;
34*4882a593Smuzhiyun 	u32 status;
35*4882a593Smuzhiyun 	u32 guardtime;
36*4882a593Smuzhiyun 	u32 timeout;
37*4882a593Smuzhiyun 	u32 txreset;
38*4882a593Smuzhiyun 	u32 rxreset;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct sti_asc_serial {
42*4882a593Smuzhiyun 	/* address of registers in physical memory */
43*4882a593Smuzhiyun 	struct sti_asc_uart *regs;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* Values for the BAUDRATE Register */
47*4882a593Smuzhiyun #define PCLK			(200ul * 1000000ul)
48*4882a593Smuzhiyun #define BAUDRATE_VAL_M0(bps)	(PCLK / (16 * (bps)))
49*4882a593Smuzhiyun #define BAUDRATE_VAL_M1(bps)	((bps * (1 << 14)) + (1<<13)) / (PCLK/(1 << 6))
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun  * MODE 0
53*4882a593Smuzhiyun  *                       ICCLK
54*4882a593Smuzhiyun  * ASCBaudRate =   ----------------
55*4882a593Smuzhiyun  *                   baudrate * 16
56*4882a593Smuzhiyun  *
57*4882a593Smuzhiyun  * MODE 1
58*4882a593Smuzhiyun  *                   baudrate * 16 * 2^16
59*4882a593Smuzhiyun  * ASCBaudRate =   ------------------------
60*4882a593Smuzhiyun  *                          ICCLK
61*4882a593Smuzhiyun  *
62*4882a593Smuzhiyun  * NOTE:
63*4882a593Smuzhiyun  * Mode 1 should be used for baudrates of 19200, and above, as it
64*4882a593Smuzhiyun  * has a lower deviation error than Mode 0 for higher frequencies.
65*4882a593Smuzhiyun  * Mode 0 should be used for all baudrates below 19200.
66*4882a593Smuzhiyun  */
67*4882a593Smuzhiyun 
sti_asc_pending(struct udevice * dev,bool input)68*4882a593Smuzhiyun static int sti_asc_pending(struct udevice *dev, bool input)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	struct sti_asc_serial *priv = dev_get_priv(dev);
71*4882a593Smuzhiyun 	struct sti_asc_uart *const uart = priv->regs;
72*4882a593Smuzhiyun 	unsigned long status;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	status = readl(&uart->status);
75*4882a593Smuzhiyun 	if (input)
76*4882a593Smuzhiyun 		return status & STA_RBF;
77*4882a593Smuzhiyun 	else
78*4882a593Smuzhiyun 		return status & STA_TF;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
_sti_asc_serial_setbrg(struct sti_asc_uart * uart,int baudrate)81*4882a593Smuzhiyun static int _sti_asc_serial_setbrg(struct sti_asc_uart *uart, int baudrate)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	unsigned long val;
84*4882a593Smuzhiyun 	int t, mode = 1;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	switch (baudrate) {
87*4882a593Smuzhiyun 	case 9600:
88*4882a593Smuzhiyun 		t = BAUDRATE_VAL_M0(9600);
89*4882a593Smuzhiyun 		mode = 0;
90*4882a593Smuzhiyun 		break;
91*4882a593Smuzhiyun 	case 19200:
92*4882a593Smuzhiyun 		t = BAUDRATE_VAL_M1(19200);
93*4882a593Smuzhiyun 		break;
94*4882a593Smuzhiyun 	case 38400:
95*4882a593Smuzhiyun 		t = BAUDRATE_VAL_M1(38400);
96*4882a593Smuzhiyun 		break;
97*4882a593Smuzhiyun 	case 57600:
98*4882a593Smuzhiyun 		t = BAUDRATE_VAL_M1(57600);
99*4882a593Smuzhiyun 		break;
100*4882a593Smuzhiyun 	default:
101*4882a593Smuzhiyun 		debug("ASC: unsupported baud rate: %d, using 115200 instead.\n",
102*4882a593Smuzhiyun 		      baudrate);
103*4882a593Smuzhiyun 	case 115200:
104*4882a593Smuzhiyun 		t = BAUDRATE_VAL_M1(115200);
105*4882a593Smuzhiyun 		break;
106*4882a593Smuzhiyun 	}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/* disable the baudrate generator */
109*4882a593Smuzhiyun 	val = readl(&uart->control);
110*4882a593Smuzhiyun 	writel(val & ~RUN, &uart->control);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* set baud generator reload value */
113*4882a593Smuzhiyun 	writel(t, &uart->baudrate);
114*4882a593Smuzhiyun 	/* reset the RX & TX buffers */
115*4882a593Smuzhiyun 	writel(1, &uart->txreset);
116*4882a593Smuzhiyun 	writel(1, &uart->rxreset);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* set baud generator mode */
119*4882a593Smuzhiyun 	if (mode)
120*4882a593Smuzhiyun 		val |= BAUDMODE;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* finally, write value and enable ASC */
123*4882a593Smuzhiyun 	writel(val, &uart->control);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun /* called to adjust baud-rate */
sti_asc_serial_setbrg(struct udevice * dev,int baudrate)129*4882a593Smuzhiyun static int sti_asc_serial_setbrg(struct udevice *dev, int baudrate)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct sti_asc_serial *priv = dev_get_priv(dev);
132*4882a593Smuzhiyun 	struct sti_asc_uart *const uart = priv->regs;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	return _sti_asc_serial_setbrg(uart, baudrate);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* blocking function, that returns next char */
sti_asc_serial_getc(struct udevice * dev)138*4882a593Smuzhiyun static int sti_asc_serial_getc(struct udevice *dev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	struct sti_asc_serial *priv = dev_get_priv(dev);
141*4882a593Smuzhiyun 	struct sti_asc_uart *const uart = priv->regs;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* polling wait: for a char to be read */
144*4882a593Smuzhiyun 	if (!sti_asc_pending(dev, true))
145*4882a593Smuzhiyun 		return -EAGAIN;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return readl(&uart->rxbuf);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* write write out a single char */
sti_asc_serial_putc(struct udevice * dev,const char c)151*4882a593Smuzhiyun static int sti_asc_serial_putc(struct udevice *dev, const char c)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct sti_asc_serial *priv = dev_get_priv(dev);
154*4882a593Smuzhiyun 	struct sti_asc_uart *const uart = priv->regs;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* wait till safe to write next char */
157*4882a593Smuzhiyun 	if (sti_asc_pending(dev, false))
158*4882a593Smuzhiyun 		return -EAGAIN;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* finally, write next char */
161*4882a593Smuzhiyun 	writel(c, &uart->txbuf);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /* initialize the ASC */
sti_asc_serial_probe(struct udevice * dev)167*4882a593Smuzhiyun static int sti_asc_serial_probe(struct udevice *dev)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	struct sti_asc_serial *priv = dev_get_priv(dev);
170*4882a593Smuzhiyun 	unsigned long val;
171*4882a593Smuzhiyun 	fdt_addr_t base;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	base = devfdt_get_addr(dev);
174*4882a593Smuzhiyun 	if (base == FDT_ADDR_T_NONE)
175*4882a593Smuzhiyun 		return -EINVAL;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	priv->regs = (struct sti_asc_uart *)base;
178*4882a593Smuzhiyun 	sti_asc_serial_setbrg(dev, gd->baudrate);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/*
181*4882a593Smuzhiyun 	 * build up the value to be written to CONTROL
182*4882a593Smuzhiyun 	 * set character length, bit stop number, odd parity
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	val = RXENABLE | RUN | MODE_8BIT | STOP_1BIT | PARITYODD;
185*4882a593Smuzhiyun 	writel(val, &priv->regs->control);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct dm_serial_ops sti_asc_serial_ops = {
191*4882a593Smuzhiyun 	.putc = sti_asc_serial_putc,
192*4882a593Smuzhiyun 	.pending = sti_asc_pending,
193*4882a593Smuzhiyun 	.getc = sti_asc_serial_getc,
194*4882a593Smuzhiyun 	.setbrg = sti_asc_serial_setbrg,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun static const struct udevice_id sti_serial_of_match[] = {
198*4882a593Smuzhiyun 	{ .compatible = "st,asc" },
199*4882a593Smuzhiyun 	{ }
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun U_BOOT_DRIVER(serial_sti_asc) = {
203*4882a593Smuzhiyun 	.name = "serial_sti_asc",
204*4882a593Smuzhiyun 	.id = UCLASS_SERIAL,
205*4882a593Smuzhiyun 	.of_match = sti_serial_of_match,
206*4882a593Smuzhiyun 	.ops = &sti_asc_serial_ops,
207*4882a593Smuzhiyun 	.probe = sti_asc_serial_probe,
208*4882a593Smuzhiyun 	.priv_auto_alloc_size = sizeof(struct sti_asc_serial),
209*4882a593Smuzhiyun 	.flags = DM_FLAG_PRE_RELOC,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212