1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <serial.h>
11*4882a593Smuzhiyun #include <wait_bit.h>
12*4882a593Smuzhiyun #include <mach/pic32.h>
13*4882a593Smuzhiyun #include <dt-bindings/clock/microchip,clock.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* UART Control Registers */
18*4882a593Smuzhiyun #define U_MOD 0x00
19*4882a593Smuzhiyun #define U_MODCLR (U_MOD + _CLR_OFFSET)
20*4882a593Smuzhiyun #define U_MODSET (U_MOD + _SET_OFFSET)
21*4882a593Smuzhiyun #define U_STA 0x10
22*4882a593Smuzhiyun #define U_STACLR (U_STA + _CLR_OFFSET)
23*4882a593Smuzhiyun #define U_STASET (U_STA + _SET_OFFSET)
24*4882a593Smuzhiyun #define U_TXR 0x20
25*4882a593Smuzhiyun #define U_RXR 0x30
26*4882a593Smuzhiyun #define U_BRG 0x40
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* U_MOD bits */
29*4882a593Smuzhiyun #define UART_ENABLE BIT(15)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* U_STA bits */
32*4882a593Smuzhiyun #define UART_RX_ENABLE BIT(12)
33*4882a593Smuzhiyun #define UART_TX_BRK BIT(11)
34*4882a593Smuzhiyun #define UART_TX_ENABLE BIT(10)
35*4882a593Smuzhiyun #define UART_TX_FULL BIT(9)
36*4882a593Smuzhiyun #define UART_TX_EMPTY BIT(8)
37*4882a593Smuzhiyun #define UART_RX_OVER BIT(1)
38*4882a593Smuzhiyun #define UART_RX_DATA_AVAIL BIT(0)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct pic32_uart_priv {
41*4882a593Smuzhiyun void __iomem *base;
42*4882a593Smuzhiyun ulong uartclk;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * Initialize the serial port with the given baudrate.
47*4882a593Smuzhiyun * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
48*4882a593Smuzhiyun */
pic32_serial_init(void __iomem * base,ulong clk,u32 baudrate)49*4882a593Smuzhiyun static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* wait for TX FIFO to empty */
54*4882a593Smuzhiyun wait_for_bit_le32(base + U_STA, UART_TX_EMPTY,
55*4882a593Smuzhiyun true, CONFIG_SYS_HZ, false);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* send break */
58*4882a593Smuzhiyun writel(UART_TX_BRK, base + U_STASET);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* disable and clear mode */
61*4882a593Smuzhiyun writel(0, base + U_MOD);
62*4882a593Smuzhiyun writel(0, base + U_STA);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* set baud rate generator */
65*4882a593Smuzhiyun writel(div - 1, base + U_BRG);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* enable the UART for TX and RX */
68*4882a593Smuzhiyun writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* enable the UART */
71*4882a593Smuzhiyun writel(UART_ENABLE, base + U_MODSET);
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Check whether any char pending in RX fifo */
pic32_uart_pending_input(void __iomem * base)76*4882a593Smuzhiyun static int pic32_uart_pending_input(void __iomem *base)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun /* check if rx buffer overrun error has occurred */
79*4882a593Smuzhiyun if (readl(base + U_STA) & UART_RX_OVER) {
80*4882a593Smuzhiyun readl(base + U_RXR);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* clear overrun error to keep receiving */
83*4882a593Smuzhiyun writel(UART_RX_OVER, base + U_STACLR);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* In PIC32 there is no way to know number of outstanding
87*4882a593Smuzhiyun * chars in rx-fifo. Only it can be known whether there is any.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun return readl(base + U_STA) & UART_RX_DATA_AVAIL;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
pic32_uart_pending(struct udevice * dev,bool input)92*4882a593Smuzhiyun static int pic32_uart_pending(struct udevice *dev, bool input)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct pic32_uart_priv *priv = dev_get_priv(dev);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (input)
97*4882a593Smuzhiyun return pic32_uart_pending_input(priv->base);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return !(readl(priv->base + U_STA) & UART_TX_EMPTY);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
pic32_uart_setbrg(struct udevice * dev,int baudrate)102*4882a593Smuzhiyun static int pic32_uart_setbrg(struct udevice *dev, int baudrate)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct pic32_uart_priv *priv = dev_get_priv(dev);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return pic32_serial_init(priv->base, priv->uartclk, baudrate);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
pic32_uart_putc(struct udevice * dev,const char ch)109*4882a593Smuzhiyun static int pic32_uart_putc(struct udevice *dev, const char ch)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun struct pic32_uart_priv *priv = dev_get_priv(dev);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Check if Tx FIFO is full */
114*4882a593Smuzhiyun if (readl(priv->base + U_STA) & UART_TX_FULL)
115*4882a593Smuzhiyun return -EAGAIN;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* pump the char to tx buffer */
118*4882a593Smuzhiyun writel(ch, priv->base + U_TXR);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
pic32_uart_getc(struct udevice * dev)123*4882a593Smuzhiyun static int pic32_uart_getc(struct udevice *dev)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct pic32_uart_priv *priv = dev_get_priv(dev);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* return error if RX fifo is empty */
128*4882a593Smuzhiyun if (!pic32_uart_pending_input(priv->base))
129*4882a593Smuzhiyun return -EAGAIN;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* read the character from rx buffer */
132*4882a593Smuzhiyun return readl(priv->base + U_RXR) & 0xff;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
pic32_uart_probe(struct udevice * dev)135*4882a593Smuzhiyun static int pic32_uart_probe(struct udevice *dev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun struct pic32_uart_priv *priv = dev_get_priv(dev);
138*4882a593Smuzhiyun struct clk clk;
139*4882a593Smuzhiyun fdt_addr_t addr;
140*4882a593Smuzhiyun fdt_size_t size;
141*4882a593Smuzhiyun int ret;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* get address */
144*4882a593Smuzhiyun addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
145*4882a593Smuzhiyun &size);
146*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
147*4882a593Smuzhiyun return -EINVAL;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun priv->base = ioremap(addr, size);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* get clock rate */
152*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &clk);
153*4882a593Smuzhiyun if (ret < 0)
154*4882a593Smuzhiyun return ret;
155*4882a593Smuzhiyun priv->uartclk = clk_get_rate(&clk);
156*4882a593Smuzhiyun clk_free(&clk);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* initialize serial */
159*4882a593Smuzhiyun return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct dm_serial_ops pic32_uart_ops = {
163*4882a593Smuzhiyun .putc = pic32_uart_putc,
164*4882a593Smuzhiyun .pending = pic32_uart_pending,
165*4882a593Smuzhiyun .getc = pic32_uart_getc,
166*4882a593Smuzhiyun .setbrg = pic32_uart_setbrg,
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const struct udevice_id pic32_uart_ids[] = {
170*4882a593Smuzhiyun { .compatible = "microchip,pic32mzda-uart" },
171*4882a593Smuzhiyun {}
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun U_BOOT_DRIVER(pic32_serial) = {
175*4882a593Smuzhiyun .name = "pic32-uart",
176*4882a593Smuzhiyun .id = UCLASS_SERIAL,
177*4882a593Smuzhiyun .of_match = pic32_uart_ids,
178*4882a593Smuzhiyun .probe = pic32_uart_probe,
179*4882a593Smuzhiyun .ops = &pic32_uart_ops,
180*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
181*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct pic32_uart_priv),
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART_PIC32
185*4882a593Smuzhiyun #include <debug_uart.h>
186*4882a593Smuzhiyun
_debug_uart_init(void)187*4882a593Smuzhiyun static inline void _debug_uart_init(void)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
_debug_uart_putc(int ch)194*4882a593Smuzhiyun static inline void _debug_uart_putc(int ch)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun DEBUG_UART_FUNCS
200*4882a593Smuzhiyun #endif
201