1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <ns16550.h>
10*4882a593Smuzhiyun #include <serial.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * The UART clock is calculated as
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * UART clock = XTAL * UART_MUL / UART_DIV
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * The baudrate is calculated as
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * baud rate = UART clock / UART_PS / DLAB
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun #define UART_PS 0x30
22*4882a593Smuzhiyun #define UART_MUL 0x34
23*4882a593Smuzhiyun #define UART_DIV 0x38
24*4882a593Smuzhiyun
mid_writel(struct ns16550_platdata * plat,int offset,int value)25*4882a593Smuzhiyun static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned char *addr;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun offset *= 1 << plat->reg_shift;
30*4882a593Smuzhiyun addr = (unsigned char *)plat->base + offset;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun writel(value, addr + plat->reg_offset);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
mid_serial_probe(struct udevice * dev)35*4882a593Smuzhiyun static int mid_serial_probe(struct udevice *dev)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct ns16550_platdata *plat = dev_get_platdata(dev);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * Initialize fractional divider correctly for Intel Edison
41*4882a593Smuzhiyun * platform.
42*4882a593Smuzhiyun *
43*4882a593Smuzhiyun * For backward compatibility we have to set initial DLAB value
44*4882a593Smuzhiyun * to 16 and speed to 115200 baud, where initial frequency is
45*4882a593Smuzhiyun * 29491200Hz, and XTAL frequency is 38.4MHz.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun mid_writel(plat, UART_MUL, 96);
48*4882a593Smuzhiyun mid_writel(plat, UART_DIV, 125);
49*4882a593Smuzhiyun mid_writel(plat, UART_PS, 16);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return ns16550_serial_probe(dev);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct udevice_id mid_serial_ids[] = {
55*4882a593Smuzhiyun { .compatible = "intel,mid-uart" },
56*4882a593Smuzhiyun {}
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun U_BOOT_DRIVER(serial_intel_mid) = {
60*4882a593Smuzhiyun .name = "serial_intel_mid",
61*4882a593Smuzhiyun .id = UCLASS_SERIAL,
62*4882a593Smuzhiyun .of_match = mid_serial_ids,
63*4882a593Smuzhiyun .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
64*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
65*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct NS16550),
66*4882a593Smuzhiyun .probe = mid_serial_probe,
67*4882a593Smuzhiyun .ops = &ns16550_serial_ops,
68*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
69*4882a593Smuzhiyun };
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