1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <serial.h>
10*4882a593Smuzhiyun #include <dm/platform_data/lpc32xx_hsuart.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/arch/uart.h>
13*4882a593Smuzhiyun #include <linux/compiler.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct lpc32xx_hsuart_priv {
18*4882a593Smuzhiyun struct hsuart_regs *hsuart;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
lpc32xx_serial_setbrg(struct udevice * dev,int baudrate)21*4882a593Smuzhiyun static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
24*4882a593Smuzhiyun struct hsuart_regs *hsuart = priv->hsuart;
25*4882a593Smuzhiyun u32 div;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
28*4882a593Smuzhiyun div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
29*4882a593Smuzhiyun if (div > 255)
30*4882a593Smuzhiyun div = 255;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun writel(div, &hsuart->rate);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return 0;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
lpc32xx_serial_getc(struct udevice * dev)37*4882a593Smuzhiyun static int lpc32xx_serial_getc(struct udevice *dev)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
40*4882a593Smuzhiyun struct hsuart_regs *hsuart = priv->hsuart;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
43*4882a593Smuzhiyun return -EAGAIN;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return readl(&hsuart->rx) & HSUART_RX_DATA;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
lpc32xx_serial_putc(struct udevice * dev,const char c)48*4882a593Smuzhiyun static int lpc32xx_serial_putc(struct udevice *dev, const char c)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
51*4882a593Smuzhiyun struct hsuart_regs *hsuart = priv->hsuart;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Wait for empty FIFO */
54*4882a593Smuzhiyun if (readl(&hsuart->level) & HSUART_LEVEL_TX)
55*4882a593Smuzhiyun return -EAGAIN;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun writel(c, &hsuart->tx);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
lpc32xx_serial_pending(struct udevice * dev,bool input)62*4882a593Smuzhiyun static int lpc32xx_serial_pending(struct udevice *dev, bool input)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
65*4882a593Smuzhiyun struct hsuart_regs *hsuart = priv->hsuart;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (input) {
68*4882a593Smuzhiyun if (readl(&hsuart->level) & HSUART_LEVEL_RX)
69*4882a593Smuzhiyun return 1;
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun if (readl(&hsuart->level) & HSUART_LEVEL_TX)
72*4882a593Smuzhiyun return 1;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
lpc32xx_serial_init(struct hsuart_regs * hsuart)78*4882a593Smuzhiyun static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
81*4882a593Smuzhiyun writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
82*4882a593Smuzhiyun HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
83*4882a593Smuzhiyun &hsuart->ctrl);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
lpc32xx_hsuart_probe(struct udevice * dev)88*4882a593Smuzhiyun static int lpc32xx_hsuart_probe(struct udevice *dev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct lpc32xx_hsuart_platdata *platdata = dev_get_platdata(dev);
91*4882a593Smuzhiyun struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun priv->hsuart = (struct hsuart_regs *)platdata->base;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun lpc32xx_serial_init(priv->hsuart);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct dm_serial_ops lpc32xx_hsuart_ops = {
101*4882a593Smuzhiyun .setbrg = lpc32xx_serial_setbrg,
102*4882a593Smuzhiyun .getc = lpc32xx_serial_getc,
103*4882a593Smuzhiyun .putc = lpc32xx_serial_putc,
104*4882a593Smuzhiyun .pending = lpc32xx_serial_pending,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun U_BOOT_DRIVER(lpc32xx_hsuart) = {
108*4882a593Smuzhiyun .name = "lpc32xx_hsuart",
109*4882a593Smuzhiyun .id = UCLASS_SERIAL,
110*4882a593Smuzhiyun .probe = lpc32xx_hsuart_probe,
111*4882a593Smuzhiyun .ops = &lpc32xx_hsuart_ops,
112*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct lpc32xx_hsuart_priv),
113*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
114*4882a593Smuzhiyun };
115