1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3*4882a593Smuzhiyun * Scott McNutt <smcnutt@psyent.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <serial.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* status register */
17*4882a593Smuzhiyun #define ALTERA_UART_TMT BIT(5) /* tx empty */
18*4882a593Smuzhiyun #define ALTERA_UART_TRDY BIT(6) /* tx ready */
19*4882a593Smuzhiyun #define ALTERA_UART_RRDY BIT(7) /* rx ready */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct altera_uart_regs {
22*4882a593Smuzhiyun u32 rxdata; /* Rx data reg */
23*4882a593Smuzhiyun u32 txdata; /* Tx data reg */
24*4882a593Smuzhiyun u32 status; /* Status reg */
25*4882a593Smuzhiyun u32 control; /* Control reg */
26*4882a593Smuzhiyun u32 divisor; /* Baud rate divisor reg */
27*4882a593Smuzhiyun u32 endofpacket; /* End-of-packet reg */
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct altera_uart_platdata {
31*4882a593Smuzhiyun struct altera_uart_regs *regs;
32*4882a593Smuzhiyun unsigned int uartclk;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
altera_uart_setbrg(struct udevice * dev,int baudrate)35*4882a593Smuzhiyun static int altera_uart_setbrg(struct udevice *dev, int baudrate)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun struct altera_uart_platdata *plat = dev->platdata;
38*4882a593Smuzhiyun struct altera_uart_regs *const regs = plat->regs;
39*4882a593Smuzhiyun u32 div;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun div = (plat->uartclk / baudrate) - 1;
42*4882a593Smuzhiyun writel(div, ®s->divisor);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
altera_uart_putc(struct udevice * dev,const char ch)47*4882a593Smuzhiyun static int altera_uart_putc(struct udevice *dev, const char ch)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct altera_uart_platdata *plat = dev->platdata;
50*4882a593Smuzhiyun struct altera_uart_regs *const regs = plat->regs;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun if (!(readl(®s->status) & ALTERA_UART_TRDY))
53*4882a593Smuzhiyun return -EAGAIN;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun writel(ch, ®s->txdata);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
altera_uart_pending(struct udevice * dev,bool input)60*4882a593Smuzhiyun static int altera_uart_pending(struct udevice *dev, bool input)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct altera_uart_platdata *plat = dev->platdata;
63*4882a593Smuzhiyun struct altera_uart_regs *const regs = plat->regs;
64*4882a593Smuzhiyun u32 st = readl(®s->status);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (input)
67*4882a593Smuzhiyun return st & ALTERA_UART_RRDY ? 1 : 0;
68*4882a593Smuzhiyun else
69*4882a593Smuzhiyun return !(st & ALTERA_UART_TMT);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
altera_uart_getc(struct udevice * dev)72*4882a593Smuzhiyun static int altera_uart_getc(struct udevice *dev)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct altera_uart_platdata *plat = dev->platdata;
75*4882a593Smuzhiyun struct altera_uart_regs *const regs = plat->regs;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (!(readl(®s->status) & ALTERA_UART_RRDY))
78*4882a593Smuzhiyun return -EAGAIN;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return readl(®s->rxdata) & 0xff;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
altera_uart_probe(struct udevice * dev)83*4882a593Smuzhiyun static int altera_uart_probe(struct udevice *dev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
altera_uart_ofdata_to_platdata(struct udevice * dev)88*4882a593Smuzhiyun static int altera_uart_ofdata_to_platdata(struct udevice *dev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct altera_uart_platdata *plat = dev_get_platdata(dev);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun plat->regs = map_physmem(devfdt_get_addr(dev),
93*4882a593Smuzhiyun sizeof(struct altera_uart_regs),
94*4882a593Smuzhiyun MAP_NOCACHE);
95*4882a593Smuzhiyun plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
96*4882a593Smuzhiyun "clock-frequency", 0);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct dm_serial_ops altera_uart_ops = {
102*4882a593Smuzhiyun .putc = altera_uart_putc,
103*4882a593Smuzhiyun .pending = altera_uart_pending,
104*4882a593Smuzhiyun .getc = altera_uart_getc,
105*4882a593Smuzhiyun .setbrg = altera_uart_setbrg,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct udevice_id altera_uart_ids[] = {
109*4882a593Smuzhiyun { .compatible = "altr,uart-1.0" },
110*4882a593Smuzhiyun {}
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun U_BOOT_DRIVER(altera_uart) = {
114*4882a593Smuzhiyun .name = "altera_uart",
115*4882a593Smuzhiyun .id = UCLASS_SERIAL,
116*4882a593Smuzhiyun .of_match = altera_uart_ids,
117*4882a593Smuzhiyun .ofdata_to_platdata = altera_uart_ofdata_to_platdata,
118*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct altera_uart_platdata),
119*4882a593Smuzhiyun .probe = altera_uart_probe,
120*4882a593Smuzhiyun .ops = &altera_uart_ops,
121*4882a593Smuzhiyun .flags = DM_FLAG_PRE_RELOC,
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART_ALTERA_UART
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #include <debug_uart.h>
127*4882a593Smuzhiyun
_debug_uart_init(void)128*4882a593Smuzhiyun static inline void _debug_uart_init(void)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
131*4882a593Smuzhiyun u32 div;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
134*4882a593Smuzhiyun writel(div, ®s->divisor);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
_debug_uart_putc(int ch)137*4882a593Smuzhiyun static inline void _debug_uart_putc(int ch)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun while (1) {
142*4882a593Smuzhiyun u32 st = readl(®s->status);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (st & ALTERA_UART_TRDY)
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun writel(ch, ®s->txdata);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun DEBUG_UART_FUNCS
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun #endif
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