1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007
3*4882a593Smuzhiyun * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * Epson RX8025 RTC driver.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <command.h>
14*4882a593Smuzhiyun #include <rtc.h>
15*4882a593Smuzhiyun #include <i2c.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
20*4882a593Smuzhiyun #undef DEBUG_RTC
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef DEBUG_RTC
23*4882a593Smuzhiyun #define DEBUGR(fmt,args...) printf(fmt ,##args)
24*4882a593Smuzhiyun #else
25*4882a593Smuzhiyun #define DEBUGR(fmt,args...)
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_RTC_ADDR
30*4882a593Smuzhiyun # define CONFIG_SYS_I2C_RTC_ADDR 0x32
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * RTC register addresses
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x00
37*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x01
38*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x02
39*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x03
40*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x04
41*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x05
42*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x06
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define RTC_CTL1_REG_ADDR 0x0e
45*4882a593Smuzhiyun #define RTC_CTL2_REG_ADDR 0x0f
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Control register 1 bits
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun #define RTC_CTL1_BIT_2412 0x20
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * Control register 2 bits
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun #define RTC_CTL2_BIT_PON 0x10
56*4882a593Smuzhiyun #define RTC_CTL2_BIT_VDET 0x40
57*4882a593Smuzhiyun #define RTC_CTL2_BIT_XST 0x20
58*4882a593Smuzhiyun #define RTC_CTL2_BIT_VDSL 0x80
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Note: the RX8025 I2C RTC requires register
62*4882a593Smuzhiyun * reads and write to consist of a single bus
63*4882a593Smuzhiyun * cycle. It is not allowed to write the register
64*4882a593Smuzhiyun * address in a first cycle that is terminated by
65*4882a593Smuzhiyun * a STOP condition. The chips needs a 'restart'
66*4882a593Smuzhiyun * sequence (start sequence without a prior stop).
67*4882a593Smuzhiyun * This driver has been written for a 4xx board.
68*4882a593Smuzhiyun * U-Boot's 4xx i2c driver is currently not capable
69*4882a593Smuzhiyun * to generate such cycles to some work arounds
70*4882a593Smuzhiyun * are used.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* static uchar rtc_read (uchar reg); */
74*4882a593Smuzhiyun #define rtc_read(reg) buf[((reg) + 1) & 0xf]
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * Get the current time from the RTC
80*4882a593Smuzhiyun */
rtc_get(struct rtc_time * tmp)81*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int rel = 0;
84*4882a593Smuzhiyun uchar sec, min, hour, mday, wday, mon, year, ctl2;
85*4882a593Smuzhiyun uchar buf[16];
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
88*4882a593Smuzhiyun printf("Error reading from RTC\n");
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun sec = rtc_read(RTC_SEC_REG_ADDR);
91*4882a593Smuzhiyun min = rtc_read(RTC_MIN_REG_ADDR);
92*4882a593Smuzhiyun hour = rtc_read(RTC_HR_REG_ADDR);
93*4882a593Smuzhiyun wday = rtc_read(RTC_DAY_REG_ADDR);
94*4882a593Smuzhiyun mday = rtc_read(RTC_DATE_REG_ADDR);
95*4882a593Smuzhiyun mon = rtc_read(RTC_MON_REG_ADDR);
96*4882a593Smuzhiyun year = rtc_read(RTC_YR_REG_ADDR);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
99*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x\n",
100*4882a593Smuzhiyun year, mon, mday, wday, hour, min, sec);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* dump status */
103*4882a593Smuzhiyun ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
104*4882a593Smuzhiyun if (ctl2 & RTC_CTL2_BIT_PON) {
105*4882a593Smuzhiyun printf("RTC: power-on detected\n");
106*4882a593Smuzhiyun rel = -1;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (ctl2 & RTC_CTL2_BIT_VDET) {
110*4882a593Smuzhiyun printf("RTC: voltage drop detected\n");
111*4882a593Smuzhiyun rel = -1;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (!(ctl2 & RTC_CTL2_BIT_XST)) {
115*4882a593Smuzhiyun printf("RTC: oscillator stop detected\n");
116*4882a593Smuzhiyun rel = -1;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun tmp->tm_sec = bcd2bin (sec & 0x7F);
120*4882a593Smuzhiyun tmp->tm_min = bcd2bin (min & 0x7F);
121*4882a593Smuzhiyun if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
122*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x3F);
123*4882a593Smuzhiyun else
124*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
125*4882a593Smuzhiyun ((hour & 0x20) ? 12 : 0);
126*4882a593Smuzhiyun tmp->tm_mday = bcd2bin (mday & 0x3F);
127*4882a593Smuzhiyun tmp->tm_mon = bcd2bin (mon & 0x1F);
128*4882a593Smuzhiyun tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
129*4882a593Smuzhiyun tmp->tm_wday = bcd2bin (wday & 0x07);
130*4882a593Smuzhiyun tmp->tm_yday = 0;
131*4882a593Smuzhiyun tmp->tm_isdst= 0;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
134*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
135*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return rel;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * Set the RTC
142*4882a593Smuzhiyun */
rtc_set(struct rtc_time * tmp)143*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
146*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
147*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
150*4882a593Smuzhiyun printf("WARNING: year should be between 1970 and 2069!\n");
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
153*4882a593Smuzhiyun rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
154*4882a593Smuzhiyun rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
155*4882a593Smuzhiyun rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
156*4882a593Smuzhiyun rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
157*4882a593Smuzhiyun rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
158*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * Reset the RTC. We setting the date back to 1970-01-01.
167*4882a593Smuzhiyun */
rtc_reset(void)168*4882a593Smuzhiyun void rtc_reset (void)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct rtc_time tmp;
171*4882a593Smuzhiyun uchar buf[16];
172*4882a593Smuzhiyun uchar ctl2;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
175*4882a593Smuzhiyun printf("Error reading from RTC\n");
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
178*4882a593Smuzhiyun ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
179*4882a593Smuzhiyun ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
180*4882a593Smuzhiyun rtc_write (RTC_CTL2_REG_ADDR, ctl2);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun tmp.tm_year = 1970;
183*4882a593Smuzhiyun tmp.tm_mon = 1;
184*4882a593Smuzhiyun tmp.tm_mday= 1;
185*4882a593Smuzhiyun tmp.tm_hour = 0;
186*4882a593Smuzhiyun tmp.tm_min = 0;
187*4882a593Smuzhiyun tmp.tm_sec = 0;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun rtc_set(&tmp);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
192*4882a593Smuzhiyun tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
193*4882a593Smuzhiyun tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun * Helper functions
200*4882a593Smuzhiyun */
rtc_write(uchar reg,uchar val)201*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun uchar buf[2];
204*4882a593Smuzhiyun buf[0] = reg << 4;
205*4882a593Smuzhiyun buf[1] = val;
206*4882a593Smuzhiyun if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
207*4882a593Smuzhiyun printf("Error writing to RTC\n");
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */
212