1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <power/pmic.h>
10*4882a593Smuzhiyun #include <power/rk8xx_pmic.h>
11*4882a593Smuzhiyun #include <irq-generic.h>
12*4882a593Smuzhiyun #include <asm/arch/periph.h>
13*4882a593Smuzhiyun #include <dm/pinctrl.h>
14*4882a593Smuzhiyun #include <rtc.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define RK817_INT_STS_REG0 0xf8
17*4882a593Smuzhiyun #define RK817_INT_MSK_REG0 0xf9
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define RK816_INT_STS_REG2 0x4c
20*4882a593Smuzhiyun #define RK816_INT_MSK_REG2 0x4d
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define RK808_INT_STS_REG1 0x4c
23*4882a593Smuzhiyun #define RK808_INT_MSK_REG1 0x4d
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define RK805_INT_STS_REG 0x4c
26*4882a593Smuzhiyun #define RK805_INT_MSK_REG 0x4d
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define RK808_RTC_CTRL_REG 0x10
29*4882a593Smuzhiyun #define RK808_RTC_STATUS_REG 0x11
30*4882a593Smuzhiyun #define RK808_RTC_INT_REG 0x12
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define RK817_RTC_CTRL_REG 0x0d
33*4882a593Smuzhiyun #define RK817_RTC_STATUS_REG 0x0e
34*4882a593Smuzhiyun #define RK817_RTC_INT_REG 0x0f
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define RTC_ALARM_EN 5
37*4882a593Smuzhiyun #define RTC_ALARM_STATUS BIT(6)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct rk8xx_rtc_priv {
40*4882a593Smuzhiyun u8 rtc_int_sts_reg;
41*4882a593Smuzhiyun u8 rtc_int_msk_reg;
42*4882a593Smuzhiyun u8 int_sts_reg;
43*4882a593Smuzhiyun u8 int_msk_reg;
44*4882a593Smuzhiyun int rtc_alarm_trigger;
45*4882a593Smuzhiyun int irq_is_busy;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
rtc_irq_handler(int irq,void * data)48*4882a593Smuzhiyun static void rtc_irq_handler(int irq, void *data)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct udevice *dev = data;
51*4882a593Smuzhiyun struct rk8xx_rtc_priv *priv = dev_get_priv(dev);
52*4882a593Smuzhiyun int ret, val;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun debug("%s: irq = %d\n", __func__, irq);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (priv->rtc_int_sts_reg) {
57*4882a593Smuzhiyun val = pmic_reg_read(dev->parent, priv->rtc_int_sts_reg);
58*4882a593Smuzhiyun if (val < 0) {
59*4882a593Smuzhiyun printf("%s: i2c read reg 0x%x failed, ret=%d\n",
60*4882a593Smuzhiyun __func__, priv->rtc_int_sts_reg, val);
61*4882a593Smuzhiyun return;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun if (val & RTC_ALARM_STATUS) {
65*4882a593Smuzhiyun priv->rtc_alarm_trigger = 1;
66*4882a593Smuzhiyun printf("RTC: alarm interrupt\n");
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun ret = pmic_reg_write(dev->parent,
70*4882a593Smuzhiyun priv->rtc_int_sts_reg, 0xfe);
71*4882a593Smuzhiyun if (ret < 0) {
72*4882a593Smuzhiyun printf("%s: i2c write reg 0x%x failed, ret=%d\n",
73*4882a593Smuzhiyun __func__, priv->rtc_int_sts_reg, ret);
74*4882a593Smuzhiyun return;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun ret = pmic_reg_write(dev->parent,
79*4882a593Smuzhiyun priv->int_sts_reg, 0xff);
80*4882a593Smuzhiyun if (ret < 0) {
81*4882a593Smuzhiyun printf("%s: i2c write reg 0x%x failed, ret=%d\n",
82*4882a593Smuzhiyun __func__, priv->int_sts_reg, ret);
83*4882a593Smuzhiyun return;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun debug("%s: reg[0x%x] = 0x%x\n", __func__, priv->int_sts_reg,
86*4882a593Smuzhiyun pmic_reg_read(dev->parent, priv->int_sts_reg));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
rtc_interrupt_init(struct udevice * dev)89*4882a593Smuzhiyun static int rtc_interrupt_init(struct udevice *dev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct rk8xx_rtc_priv *priv = dev_get_priv(dev);
92*4882a593Smuzhiyun u32 interrupt[2], phandle;
93*4882a593Smuzhiyun int irq, ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun phandle = dev_read_u32_default(dev->parent, "interrupt-parent", -1);
96*4882a593Smuzhiyun if (phandle < 0) {
97*4882a593Smuzhiyun printf("failed get 'interrupt-parent', ret=%d\n", phandle);
98*4882a593Smuzhiyun return phandle;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = dev_read_u32_array(dev->parent, "interrupts", interrupt, 2);
102*4882a593Smuzhiyun if (ret) {
103*4882a593Smuzhiyun printf("failed get 'interrupt', ret=%d\n", ret);
104*4882a593Smuzhiyun return ret;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun irq = phandle_gpio_to_irq(phandle, interrupt[0]);
108*4882a593Smuzhiyun if (irq < 0) {
109*4882a593Smuzhiyun if (irq == -EBUSY) {
110*4882a593Smuzhiyun priv->irq_is_busy = 1;
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun return irq;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun irq_install_handler(irq, rtc_irq_handler, dev);
116*4882a593Smuzhiyun irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
117*4882a593Smuzhiyun irq_handler_enable(irq);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
rk8xx_rtc_alarm_trigger(struct udevice * dev)122*4882a593Smuzhiyun static int rk8xx_rtc_alarm_trigger(struct udevice *dev)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct rk8xx_rtc_priv *priv = dev_get_priv(dev);
125*4882a593Smuzhiyun int val, ret, alarm_trigger = 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (priv->irq_is_busy) {
128*4882a593Smuzhiyun val = pmic_reg_read(dev->parent, priv->rtc_int_sts_reg);
129*4882a593Smuzhiyun if (val < 0) {
130*4882a593Smuzhiyun printf("%s: i2c read reg 0x%x failed, ret=%d\n",
131*4882a593Smuzhiyun __func__, priv->rtc_int_sts_reg, val);
132*4882a593Smuzhiyun return val;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun if (val & RTC_ALARM_STATUS) {
135*4882a593Smuzhiyun alarm_trigger = 1;
136*4882a593Smuzhiyun printf("rtc alarm interrupt\n");
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun ret = pmic_reg_write(dev->parent,
139*4882a593Smuzhiyun priv->rtc_int_sts_reg, 0xfe);
140*4882a593Smuzhiyun if (ret < 0) {
141*4882a593Smuzhiyun printf("%s: i2c write reg 0x%x failed, ret=%d\n",
142*4882a593Smuzhiyun __func__, priv->rtc_int_sts_reg, ret);
143*4882a593Smuzhiyun return ret;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun return alarm_trigger;
146*4882a593Smuzhiyun } else {
147*4882a593Smuzhiyun return priv->rtc_alarm_trigger;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static struct rtc_ops rk8xx_rtc_ops = {
152*4882a593Smuzhiyun .alarm_trigger = rk8xx_rtc_alarm_trigger,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
rk8xx_rtc_probe(struct udevice * dev)155*4882a593Smuzhiyun static int rk8xx_rtc_probe(struct udevice *dev)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct rk8xx_priv *rk8xx = dev_get_priv(dev->parent);
158*4882a593Smuzhiyun struct rk8xx_rtc_priv *priv = dev_get_priv(dev);
159*4882a593Smuzhiyun int ret, val;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun priv->rtc_int_sts_reg = RK808_RTC_STATUS_REG;
162*4882a593Smuzhiyun priv->rtc_int_msk_reg = RK808_RTC_INT_REG;
163*4882a593Smuzhiyun switch (rk8xx->variant) {
164*4882a593Smuzhiyun case RK808_ID:
165*4882a593Smuzhiyun case RK818_ID:
166*4882a593Smuzhiyun priv->int_msk_reg = RK808_INT_MSK_REG1;
167*4882a593Smuzhiyun priv->int_sts_reg = RK808_INT_STS_REG1;
168*4882a593Smuzhiyun break;
169*4882a593Smuzhiyun case RK805_ID:
170*4882a593Smuzhiyun priv->int_msk_reg = RK805_INT_MSK_REG;
171*4882a593Smuzhiyun priv->int_sts_reg = RK805_INT_STS_REG;
172*4882a593Smuzhiyun break;
173*4882a593Smuzhiyun case RK816_ID:
174*4882a593Smuzhiyun priv->int_msk_reg = RK816_INT_MSK_REG2;
175*4882a593Smuzhiyun priv->int_sts_reg = RK816_INT_STS_REG2;
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun case RK809_ID:
178*4882a593Smuzhiyun case RK817_ID:
179*4882a593Smuzhiyun priv->rtc_int_sts_reg = RK817_RTC_STATUS_REG;
180*4882a593Smuzhiyun priv->rtc_int_msk_reg = RK817_RTC_INT_REG;
181*4882a593Smuzhiyun priv->int_msk_reg = RK817_INT_MSK_REG0;
182*4882a593Smuzhiyun priv->int_sts_reg = RK817_INT_STS_REG0;
183*4882a593Smuzhiyun break;
184*4882a593Smuzhiyun default:
185*4882a593Smuzhiyun return -EINVAL;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun priv->rtc_alarm_trigger = 0;
189*4882a593Smuzhiyun priv->irq_is_busy = 0;
190*4882a593Smuzhiyun /* mask and clear interrupt */
191*4882a593Smuzhiyun val = pmic_reg_read(dev->parent, priv->int_msk_reg);
192*4882a593Smuzhiyun if (val < 0) {
193*4882a593Smuzhiyun printf("%s: i2c read reg 0x%x failed, ret=%d\n",
194*4882a593Smuzhiyun __func__, priv->int_msk_reg, val);
195*4882a593Smuzhiyun return val;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun ret = pmic_reg_write(dev->parent,
198*4882a593Smuzhiyun priv->int_msk_reg, val | 0xc1);
199*4882a593Smuzhiyun if (ret < 0) {
200*4882a593Smuzhiyun printf("%s: i2c write reg 0x%x failed, ret=%d\n",
201*4882a593Smuzhiyun __func__, priv->int_msk_reg, ret);
202*4882a593Smuzhiyun return ret;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun val = pmic_reg_read(dev->parent, priv->int_sts_reg);
205*4882a593Smuzhiyun if (val < 0) {
206*4882a593Smuzhiyun printf("%s: i2c read reg 0x%x failed, ret=%d\n",
207*4882a593Smuzhiyun __func__, priv->int_sts_reg, val);
208*4882a593Smuzhiyun return val;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun ret = pmic_reg_write(dev->parent,
211*4882a593Smuzhiyun priv->int_sts_reg,
212*4882a593Smuzhiyun val | (1 << RTC_ALARM_EN));
213*4882a593Smuzhiyun if (ret < 0) {
214*4882a593Smuzhiyun printf("%s: i2c write reg 0x%x failed, ret=%d\n",
215*4882a593Smuzhiyun __func__, priv->int_sts_reg, ret);
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun debug("%s: reg[0x%x] = 0x%x\n", __func__, priv->int_msk_reg,
219*4882a593Smuzhiyun pmic_reg_read(dev->parent, priv->int_msk_reg));
220*4882a593Smuzhiyun debug("%s: reg[0x%x] = 0x%x\n", __func__, priv->int_sts_reg,
221*4882a593Smuzhiyun pmic_reg_read(dev->parent, priv->int_sts_reg));
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return rtc_interrupt_init(dev);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun U_BOOT_DRIVER(rk8xx_rtc) = {
227*4882a593Smuzhiyun .name = "rk8xx_rtc",
228*4882a593Smuzhiyun .id = UCLASS_RTC,
229*4882a593Smuzhiyun .probe = rk8xx_rtc_probe,
230*4882a593Smuzhiyun .ops = &rk8xx_rtc_ops,
231*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rk8xx_rtc_priv),
232*4882a593Smuzhiyun };
233