1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * This file provides Date & Time support (no alarms) for PT7C4338 chip.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This file is based on drivers/rtc/ds1337.c
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * PT7C4338 chip is manufactured by Pericom Technology Inc.
15*4882a593Smuzhiyun * It is a serial real-time clock which provides
16*4882a593Smuzhiyun * 1)Low-power clock/calendar.
17*4882a593Smuzhiyun * 2)Programmable square-wave output.
18*4882a593Smuzhiyun * It has 56 bytes of nonvolatile RAM.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <common.h>
22*4882a593Smuzhiyun #include <command.h>
23*4882a593Smuzhiyun #include <rtc.h>
24*4882a593Smuzhiyun #include <i2c.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* RTC register addresses */
27*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x0
28*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x1
29*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x2
30*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x3
31*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x4
32*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x5
33*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x6
34*4882a593Smuzhiyun #define RTC_CTL_STAT_REG_ADDR 0x7
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* RTC second register address bit */
37*4882a593Smuzhiyun #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* RTC control and status register bits */
40*4882a593Smuzhiyun #define RTC_CTL_STAT_BIT_RS0 0x1 /* Rate select 0 */
41*4882a593Smuzhiyun #define RTC_CTL_STAT_BIT_RS1 0x2 /* Rate select 1 */
42*4882a593Smuzhiyun #define RTC_CTL_STAT_BIT_SQWE 0x10 /* Square Wave Enable */
43*4882a593Smuzhiyun #define RTC_CTL_STAT_BIT_OSF 0x20 /* Oscillator Stop Flag */
44*4882a593Smuzhiyun #define RTC_CTL_STAT_BIT_OUT 0x80 /* Output Level Control */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* RTC reset value */
47*4882a593Smuzhiyun #define RTC_PT7C4338_RESET_VAL \
48*4882a593Smuzhiyun (RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /****** Helper functions ****************************************/
rtc_read(u8 reg)51*4882a593Smuzhiyun static u8 rtc_read(u8 reg)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
rtc_write(u8 reg,u8 val)56*4882a593Smuzhiyun static void rtc_write(u8 reg, u8 val)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun /****************************************************************/
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Get the current time from the RTC */
rtc_get(struct rtc_time * tmp)63*4882a593Smuzhiyun int rtc_get(struct rtc_time *tmp)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun int ret = 0;
66*4882a593Smuzhiyun u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ctl_stat = rtc_read(RTC_CTL_STAT_REG_ADDR);
69*4882a593Smuzhiyun sec = rtc_read(RTC_SEC_REG_ADDR);
70*4882a593Smuzhiyun min = rtc_read(RTC_MIN_REG_ADDR);
71*4882a593Smuzhiyun hour = rtc_read(RTC_HR_REG_ADDR);
72*4882a593Smuzhiyun wday = rtc_read(RTC_DAY_REG_ADDR);
73*4882a593Smuzhiyun mday = rtc_read(RTC_DATE_REG_ADDR);
74*4882a593Smuzhiyun mon = rtc_read(RTC_MON_REG_ADDR);
75*4882a593Smuzhiyun year = rtc_read(RTC_YR_REG_ADDR);
76*4882a593Smuzhiyun debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
77*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x control_status: %02x\n",
78*4882a593Smuzhiyun year, mon, mday, wday, hour, min, sec, ctl_stat);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
81*4882a593Smuzhiyun printf("### Warning: RTC oscillator has stopped\n");
82*4882a593Smuzhiyun /* clear the OSF flag */
83*4882a593Smuzhiyun rtc_write(RTC_CTL_STAT_REG_ADDR,
84*4882a593Smuzhiyun rtc_read(RTC_CTL_STAT_REG_ADDR)\
85*4882a593Smuzhiyun & ~RTC_CTL_STAT_BIT_OSF);
86*4882a593Smuzhiyun ret = -1;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun tmp->tm_sec = bcd2bin(sec & 0x7F);
90*4882a593Smuzhiyun tmp->tm_min = bcd2bin(min & 0x7F);
91*4882a593Smuzhiyun tmp->tm_hour = bcd2bin(hour & 0x3F);
92*4882a593Smuzhiyun tmp->tm_mday = bcd2bin(mday & 0x3F);
93*4882a593Smuzhiyun tmp->tm_mon = bcd2bin(mon & 0x1F);
94*4882a593Smuzhiyun tmp->tm_year = bcd2bin(year) + 2000;
95*4882a593Smuzhiyun tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
96*4882a593Smuzhiyun tmp->tm_yday = 0;
97*4882a593Smuzhiyun tmp->tm_isdst = 0;
98*4882a593Smuzhiyun debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
99*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
100*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return ret;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Set the RTC */
rtc_set(struct rtc_time * tmp)106*4882a593Smuzhiyun int rtc_set(struct rtc_time *tmp)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
109*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
110*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
113*4882a593Smuzhiyun rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
114*4882a593Smuzhiyun rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
115*4882a593Smuzhiyun rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
116*4882a593Smuzhiyun rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
117*4882a593Smuzhiyun rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
118*4882a593Smuzhiyun rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Reset the RTC */
rtc_reset(void)124*4882a593Smuzhiyun void rtc_reset(void)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
127*4882a593Smuzhiyun rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
128*4882a593Smuzhiyun }
129