1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2001
3*4882a593Smuzhiyun * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * Date & Time support for ST Electronics M48T35Ax RTC
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*#define DEBUG */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <command.h>
17*4882a593Smuzhiyun #include <rtc.h>
18*4882a593Smuzhiyun #include <config.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
23*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */
26*4882a593Smuzhiyun
rtc_get(struct rtc_time * tmp)27*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun uchar sec, min, hour, cent_day, date, month, year;
30*4882a593Smuzhiyun uchar ccr; /* Clock control register */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Lock RTC for read using clock control register */
33*4882a593Smuzhiyun ccr = rtc_read(0);
34*4882a593Smuzhiyun ccr = ccr | 0x40;
35*4882a593Smuzhiyun rtc_write(0, ccr);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun sec = rtc_read (0x1);
38*4882a593Smuzhiyun min = rtc_read (0x2);
39*4882a593Smuzhiyun hour = rtc_read (0x3);
40*4882a593Smuzhiyun cent_day= rtc_read (0x4);
41*4882a593Smuzhiyun date = rtc_read (0x5);
42*4882a593Smuzhiyun month = rtc_read (0x6);
43*4882a593Smuzhiyun year = rtc_read (0x7);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* UNLock RTC */
46*4882a593Smuzhiyun ccr = rtc_read(0);
47*4882a593Smuzhiyun ccr = ccr & 0xBF;
48*4882a593Smuzhiyun rtc_write(0, ccr);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
51*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x\n",
52*4882a593Smuzhiyun year, month, date, cent_day,
53*4882a593Smuzhiyun hour, min, sec );
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun tmp->tm_sec = bcd2bin (sec & 0x7F);
56*4882a593Smuzhiyun tmp->tm_min = bcd2bin (min & 0x7F);
57*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x3F);
58*4882a593Smuzhiyun tmp->tm_mday = bcd2bin (date & 0x3F);
59*4882a593Smuzhiyun tmp->tm_mon = bcd2bin (month & 0x1F);
60*4882a593Smuzhiyun tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
61*4882a593Smuzhiyun tmp->tm_wday = bcd2bin (cent_day & 0x07);
62*4882a593Smuzhiyun tmp->tm_yday = 0;
63*4882a593Smuzhiyun tmp->tm_isdst= 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
66*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
67*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
rtc_set(struct rtc_time * tmp)72*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun uchar ccr; /* Clock control register */
75*4882a593Smuzhiyun uchar century;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
78*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
79*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Lock RTC for write using clock control register */
82*4882a593Smuzhiyun ccr = rtc_read(0);
83*4882a593Smuzhiyun ccr = ccr | 0x80;
84*4882a593Smuzhiyun rtc_write(0, ccr);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
87*4882a593Smuzhiyun rtc_write (0x06, bin2bcd(tmp->tm_mon));
88*4882a593Smuzhiyun rtc_write (0x05, bin2bcd(tmp->tm_mday));
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
91*4882a593Smuzhiyun rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun rtc_write (0x03, bin2bcd(tmp->tm_hour));
94*4882a593Smuzhiyun rtc_write (0x02, bin2bcd(tmp->tm_min ));
95*4882a593Smuzhiyun rtc_write (0x01, bin2bcd(tmp->tm_sec ));
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* UNLock RTC */
98*4882a593Smuzhiyun ccr = rtc_read(0);
99*4882a593Smuzhiyun ccr = ccr & 0x7F;
100*4882a593Smuzhiyun rtc_write(0, ccr);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
rtc_reset(void)105*4882a593Smuzhiyun void rtc_reset (void)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun uchar val;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Clear all clock control registers */
110*4882a593Smuzhiyun rtc_write (0x0, 0x80); /* No Read Lock or calibration */
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Clear stop bit */
113*4882a593Smuzhiyun val = rtc_read (0x1);
114*4882a593Smuzhiyun val &= 0x7f;
115*4882a593Smuzhiyun rtc_write(0x1, val);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Enable century / disable frequency test */
118*4882a593Smuzhiyun val = rtc_read (0x4);
119*4882a593Smuzhiyun val = (val & 0xBF) | 0x20;
120*4882a593Smuzhiyun rtc_write(0x4, val);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* Clear write lock */
123*4882a593Smuzhiyun rtc_write(0x0, 0);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */
127*4882a593Smuzhiyun
rtc_read(uchar reg)128*4882a593Smuzhiyun static uchar rtc_read (uchar reg)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return *(unsigned char *)
131*4882a593Smuzhiyun ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
rtc_write(uchar reg,uchar val)134*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun *(unsigned char *)
137*4882a593Smuzhiyun ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #endif
141