1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2008
3*4882a593Smuzhiyun * Tor Krill, Excito Elektronik i Skåne , tor@excito.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Modelled after the ds1337 driver
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * Date & Time support (no alarms) for Intersil
12*4882a593Smuzhiyun * ISL1208 Real Time Clock (RTC).
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <command.h>
17*4882a593Smuzhiyun #include <rtc.h>
18*4882a593Smuzhiyun #include <i2c.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
21*4882a593Smuzhiyun #ifdef DEBUG_RTC
22*4882a593Smuzhiyun #define DEBUGR(fmt,args...) printf(fmt ,##args)
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun #define DEBUGR(fmt,args...)
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * RTC register addresses
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x0
33*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x1
34*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x2
35*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x3
36*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x4
37*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x5
38*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x6
39*4882a593Smuzhiyun #define RTC_STAT_REG_ADDR 0x7
40*4882a593Smuzhiyun /*
41*4882a593Smuzhiyun * RTC control register bits
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * RTC status register bits
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
48*4882a593Smuzhiyun #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
49*4882a593Smuzhiyun #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
50*4882a593Smuzhiyun #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
51*4882a593Smuzhiyun #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
52*4882a593Smuzhiyun #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
55*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * Get the current time from the RTC
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun
rtc_get(struct rtc_time * tmp)61*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int rel = 0;
64*4882a593Smuzhiyun uchar sec, min, hour, mday, wday, mon, year, status;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun status = rtc_read (RTC_STAT_REG_ADDR);
67*4882a593Smuzhiyun sec = rtc_read (RTC_SEC_REG_ADDR);
68*4882a593Smuzhiyun min = rtc_read (RTC_MIN_REG_ADDR);
69*4882a593Smuzhiyun hour = rtc_read (RTC_HR_REG_ADDR);
70*4882a593Smuzhiyun wday = rtc_read (RTC_DAY_REG_ADDR);
71*4882a593Smuzhiyun mday = rtc_read (RTC_DATE_REG_ADDR);
72*4882a593Smuzhiyun mon = rtc_read (RTC_MON_REG_ADDR);
73*4882a593Smuzhiyun year = rtc_read (RTC_YR_REG_ADDR);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
76*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x status: %02x\n",
77*4882a593Smuzhiyun year, mon, mday, wday, hour, min, sec, status);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (status & RTC_STAT_BIT_RTCF) {
80*4882a593Smuzhiyun printf ("### Warning: RTC oscillator has stopped\n");
81*4882a593Smuzhiyun rtc_write(RTC_STAT_REG_ADDR,
82*4882a593Smuzhiyun rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
83*4882a593Smuzhiyun rel = -1;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun tmp->tm_sec = bcd2bin (sec & 0x7F);
87*4882a593Smuzhiyun tmp->tm_min = bcd2bin (min & 0x7F);
88*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x3F);
89*4882a593Smuzhiyun tmp->tm_mday = bcd2bin (mday & 0x3F);
90*4882a593Smuzhiyun tmp->tm_mon = bcd2bin (mon & 0x1F);
91*4882a593Smuzhiyun tmp->tm_year = bcd2bin (year)+2000;
92*4882a593Smuzhiyun tmp->tm_wday = bcd2bin (wday & 0x07);
93*4882a593Smuzhiyun tmp->tm_yday = 0;
94*4882a593Smuzhiyun tmp->tm_isdst= 0;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
97*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
98*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return rel;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * Set the RTC
105*4882a593Smuzhiyun */
rtc_set(struct rtc_time * tmp)106*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
109*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
110*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* enable write */
113*4882a593Smuzhiyun rtc_write(RTC_STAT_REG_ADDR,
114*4882a593Smuzhiyun rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
117*4882a593Smuzhiyun rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
118*4882a593Smuzhiyun rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
119*4882a593Smuzhiyun rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
120*4882a593Smuzhiyun rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
121*4882a593Smuzhiyun rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
122*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* disable write */
125*4882a593Smuzhiyun rtc_write(RTC_STAT_REG_ADDR,
126*4882a593Smuzhiyun rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
rtc_reset(void)131*4882a593Smuzhiyun void rtc_reset (void)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun * Helper functions
137*4882a593Smuzhiyun */
138*4882a593Smuzhiyun
rtc_read(uchar reg)139*4882a593Smuzhiyun static uchar rtc_read (uchar reg)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
rtc_write(uchar reg,uchar val)144*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
147*4882a593Smuzhiyun }
148