xref: /OK3568_Linux_fs/u-boot/drivers/rtc/ds3231.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2006
3*4882a593Smuzhiyun  * Markus Klotzbuecher, mk@denx.de
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun  * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
10*4882a593Smuzhiyun  * Extremly Accurate DS3231 Real Time Clock (RTC).
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * copied from ds1337.c
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <command.h>
17*4882a593Smuzhiyun #include <rtc.h>
18*4882a593Smuzhiyun #include <i2c.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun  * RTC register addresses
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR	0x0
26*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR	0x1
27*4882a593Smuzhiyun #define RTC_HR_REG_ADDR		0x2
28*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR	0x3
29*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR	0x4
30*4882a593Smuzhiyun #define RTC_MON_REG_ADDR	0x5
31*4882a593Smuzhiyun #define RTC_YR_REG_ADDR		0x6
32*4882a593Smuzhiyun #define RTC_CTL_REG_ADDR	0x0e
33*4882a593Smuzhiyun #define RTC_STAT_REG_ADDR	0x0f
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun  * RTC control register bits
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define RTC_CTL_BIT_A1IE	0x1	/* Alarm 1 interrupt enable     */
40*4882a593Smuzhiyun #define RTC_CTL_BIT_A2IE	0x2	/* Alarm 2 interrupt enable     */
41*4882a593Smuzhiyun #define RTC_CTL_BIT_INTCN	0x4	/* Interrupt control            */
42*4882a593Smuzhiyun #define RTC_CTL_BIT_RS1		0x8	/* Rate select 1                */
43*4882a593Smuzhiyun #define RTC_CTL_BIT_RS2		0x10	/* Rate select 2                */
44*4882a593Smuzhiyun #define RTC_CTL_BIT_DOSC	0x80	/* Disable Oscillator           */
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun  * RTC status register bits
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun #define RTC_STAT_BIT_A1F	0x1	/* Alarm 1 flag                 */
50*4882a593Smuzhiyun #define RTC_STAT_BIT_A2F	0x2	/* Alarm 2 flag                 */
51*4882a593Smuzhiyun #define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag         */
52*4882a593Smuzhiyun #define RTC_STAT_BIT_BB32KHZ	0x40	/* Battery backed 32KHz Output  */
53*4882a593Smuzhiyun #define RTC_STAT_BIT_EN32KHZ	0x8	/* Enable 32KHz Output  */
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
57*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * Get the current time from the RTC
62*4882a593Smuzhiyun  */
rtc_get(struct rtc_time * tmp)63*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	int rel = 0;
66*4882a593Smuzhiyun 	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	control = rtc_read (RTC_CTL_REG_ADDR);
69*4882a593Smuzhiyun 	status = rtc_read (RTC_STAT_REG_ADDR);
70*4882a593Smuzhiyun 	sec = rtc_read (RTC_SEC_REG_ADDR);
71*4882a593Smuzhiyun 	min = rtc_read (RTC_MIN_REG_ADDR);
72*4882a593Smuzhiyun 	hour = rtc_read (RTC_HR_REG_ADDR);
73*4882a593Smuzhiyun 	wday = rtc_read (RTC_DAY_REG_ADDR);
74*4882a593Smuzhiyun 	mday = rtc_read (RTC_DATE_REG_ADDR);
75*4882a593Smuzhiyun 	mon_cent = rtc_read (RTC_MON_REG_ADDR);
76*4882a593Smuzhiyun 	year = rtc_read (RTC_YR_REG_ADDR);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
79*4882a593Smuzhiyun 		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
80*4882a593Smuzhiyun 		year, mon_cent, mday, wday, hour, min, sec, control, status);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	if (status & RTC_STAT_BIT_OSF) {
83*4882a593Smuzhiyun 		printf ("### Warning: RTC oscillator has stopped\n");
84*4882a593Smuzhiyun 		/* clear the OSF flag */
85*4882a593Smuzhiyun 		rtc_write (RTC_STAT_REG_ADDR,
86*4882a593Smuzhiyun 			   rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
87*4882a593Smuzhiyun 		rel = -1;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	tmp->tm_sec  = bcd2bin (sec & 0x7F);
91*4882a593Smuzhiyun 	tmp->tm_min  = bcd2bin (min & 0x7F);
92*4882a593Smuzhiyun 	tmp->tm_hour = bcd2bin (hour & 0x3F);
93*4882a593Smuzhiyun 	tmp->tm_mday = bcd2bin (mday & 0x3F);
94*4882a593Smuzhiyun 	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
95*4882a593Smuzhiyun 	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
96*4882a593Smuzhiyun 	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
97*4882a593Smuzhiyun 	tmp->tm_yday = 0;
98*4882a593Smuzhiyun 	tmp->tm_isdst= 0;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
101*4882a593Smuzhiyun 		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
102*4882a593Smuzhiyun 		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	return rel;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun  * Set the RTC
110*4882a593Smuzhiyun  */
rtc_set(struct rtc_time * tmp)111*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	uchar century;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
116*4882a593Smuzhiyun 		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
117*4882a593Smuzhiyun 		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
122*4882a593Smuzhiyun 	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
125*4882a593Smuzhiyun 	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
126*4882a593Smuzhiyun 	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
127*4882a593Smuzhiyun 	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
128*4882a593Smuzhiyun 	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun  * Reset the RTC.  We also enable the oscillator output on the
136*4882a593Smuzhiyun  * SQW/INTB* pin and program it for 32,768 Hz output. Note that
137*4882a593Smuzhiyun  * according to the datasheet, turning on the square wave output
138*4882a593Smuzhiyun  * increases the current drain on the backup battery from about
139*4882a593Smuzhiyun  * 600 nA to 2uA.
140*4882a593Smuzhiyun  */
rtc_reset(void)141*4882a593Smuzhiyun void rtc_reset (void)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun  * Enable 32KHz output
148*4882a593Smuzhiyun  */
rtc_enable_32khz_output(void)149*4882a593Smuzhiyun void rtc_enable_32khz_output(void)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	rtc_write(RTC_STAT_REG_ADDR,
152*4882a593Smuzhiyun 		  RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun  * Helper functions
157*4882a593Smuzhiyun  */
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static
rtc_read(uchar reg)160*4882a593Smuzhiyun uchar rtc_read (uchar reg)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 
rtc_write(uchar reg,uchar val)166*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #endif
172