xref: /OK3568_Linux_fs/u-boot/drivers/rtc/ds1374.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2001, 2002, 2003
3*4882a593Smuzhiyun  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun  * Keith Outwater, keith_outwater@mvis.com`
5*4882a593Smuzhiyun  * Steven Scholz, steven.scholz@imc-berlin.de
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun  * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
12*4882a593Smuzhiyun  * DS1374 Real Time Clock (RTC).
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * based on ds1337.c
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <command.h>
19*4882a593Smuzhiyun #include <rtc.h>
20*4882a593Smuzhiyun #include <i2c.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
25*4882a593Smuzhiyun #undef DEBUG_RTC
26*4882a593Smuzhiyun #define DEBUG_RTC
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #ifdef DEBUG_RTC
29*4882a593Smuzhiyun #define DEBUGR(fmt,args...) printf(fmt ,##args)
30*4882a593Smuzhiyun #else
31*4882a593Smuzhiyun #define DEBUGR(fmt,args...)
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_RTC_ADDR
36*4882a593Smuzhiyun # define CONFIG_SYS_I2C_RTC_ADDR	0x68
37*4882a593Smuzhiyun #endif
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
40*4882a593Smuzhiyun # error The DS1374 is specified up to 400kHz in fast mode!
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun  * RTC register addresses
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun #define RTC_TOD_CNT_BYTE0_ADDR		0x00 /* TimeOfDay */
47*4882a593Smuzhiyun #define RTC_TOD_CNT_BYTE1_ADDR		0x01
48*4882a593Smuzhiyun #define RTC_TOD_CNT_BYTE2_ADDR		0x02
49*4882a593Smuzhiyun #define RTC_TOD_CNT_BYTE3_ADDR		0x03
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define RTC_WD_ALM_CNT_BYTE0_ADDR	0x04
52*4882a593Smuzhiyun #define RTC_WD_ALM_CNT_BYTE1_ADDR	0x05
53*4882a593Smuzhiyun #define RTC_WD_ALM_CNT_BYTE2_ADDR	0x06
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define RTC_CTL_ADDR			0x07 /* RTC-CoNTrol-register */
56*4882a593Smuzhiyun #define RTC_SR_ADDR			0x08 /* RTC-StatusRegister */
57*4882a593Smuzhiyun #define RTC_TCS_DS_ADDR			0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define RTC_CTL_BIT_AIE			(1<<0) /* Bit 0 - Alarm Interrupt enable */
60*4882a593Smuzhiyun #define RTC_CTL_BIT_RS1			(1<<1) /* Bit 1/2 - Rate Select square wave output */
61*4882a593Smuzhiyun #define RTC_CTL_BIT_RS2			(1<<2) /* Bit 2/2 - Rate Select square wave output */
62*4882a593Smuzhiyun #define RTC_CTL_BIT_WDSTR		(1<<3) /* Bit 3 - Watchdog Reset Steering */
63*4882a593Smuzhiyun #define RTC_CTL_BIT_BBSQW		(1<<4) /* Bit 4 - Battery-Backed Square-Wave */
64*4882a593Smuzhiyun #define RTC_CTL_BIT_WD_ALM		(1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
65*4882a593Smuzhiyun #define RTC_CTL_BIT_WACE		(1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
66*4882a593Smuzhiyun #define RTC_CTL_BIT_EN_OSC		(1<<7) /* Bit 7 - Enable Oscilator */
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define RTC_SR_BIT_AF			0x01 /* Bit 0 = Alarm Flag */
69*4882a593Smuzhiyun #define RTC_SR_BIT_OSF			0x80 /* Bit 7 - Osc Stop Flag */
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun const char RtcTodAddr[] = {
72*4882a593Smuzhiyun 	RTC_TOD_CNT_BYTE0_ADDR,
73*4882a593Smuzhiyun 	RTC_TOD_CNT_BYTE1_ADDR,
74*4882a593Smuzhiyun 	RTC_TOD_CNT_BYTE2_ADDR,
75*4882a593Smuzhiyun 	RTC_TOD_CNT_BYTE3_ADDR
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
79*4882a593Smuzhiyun static void rtc_write(uchar reg, uchar val, bool set);
80*4882a593Smuzhiyun static void rtc_write_raw (uchar reg, uchar val);
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun  * Get the current time from the RTC
84*4882a593Smuzhiyun  */
rtc_get(struct rtc_time * tm)85*4882a593Smuzhiyun int rtc_get (struct rtc_time *tm){
86*4882a593Smuzhiyun 	int rel = 0;
87*4882a593Smuzhiyun 	unsigned long time1, time2;
88*4882a593Smuzhiyun 	unsigned int limit;
89*4882a593Smuzhiyun 	unsigned char tmp;
90*4882a593Smuzhiyun 	unsigned int i;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	/*
93*4882a593Smuzhiyun 	 * Since the reads are being performed one byte at a time,
94*4882a593Smuzhiyun 	 * there is a chance that a carry will occur during the read.
95*4882a593Smuzhiyun 	 * To detect this, 2 reads are performed and compared.
96*4882a593Smuzhiyun 	 */
97*4882a593Smuzhiyun 	limit = 10;
98*4882a593Smuzhiyun 	do {
99*4882a593Smuzhiyun 		i = 4;
100*4882a593Smuzhiyun 		time1 = 0;
101*4882a593Smuzhiyun 		while (i--) {
102*4882a593Smuzhiyun 			tmp = rtc_read(RtcTodAddr[i]);
103*4882a593Smuzhiyun 			time1 = (time1 << 8) | (tmp & 0xff);
104*4882a593Smuzhiyun 		}
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 		i = 4;
107*4882a593Smuzhiyun 		time2 = 0;
108*4882a593Smuzhiyun 		while (i--) {
109*4882a593Smuzhiyun 			tmp = rtc_read(RtcTodAddr[i]);
110*4882a593Smuzhiyun 			time2 = (time2 << 8) | (tmp & 0xff);
111*4882a593Smuzhiyun 		}
112*4882a593Smuzhiyun 	} while ((time1 != time2) && limit--);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	if (time1 != time2) {
115*4882a593Smuzhiyun 		printf("can't get consistent time from rtc chip\n");
116*4882a593Smuzhiyun 		rel = -1;
117*4882a593Smuzhiyun 	}
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	rtc_to_tm(time1, tm); /* To Gregorian Date */
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
124*4882a593Smuzhiyun 		printf ("### Warning: RTC oscillator has stopped\n");
125*4882a593Smuzhiyun 		rel = -1;
126*4882a593Smuzhiyun 	}
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
129*4882a593Smuzhiyun 		tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
130*4882a593Smuzhiyun 		tm->tm_hour, tm->tm_min, tm->tm_sec);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return rel;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun  * Set the RTC
137*4882a593Smuzhiyun  */
rtc_set(struct rtc_time * tmp)138*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp){
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	unsigned long time;
141*4882a593Smuzhiyun 	unsigned i;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
144*4882a593Smuzhiyun 		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
145*4882a593Smuzhiyun 		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
148*4882a593Smuzhiyun 		printf("WARNING: year should be between 1970 and 2069!\n");
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	time = rtc_mktime(tmp);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* write to RTC_TOD_CNT_BYTEn_ADDR */
155*4882a593Smuzhiyun 	for (i = 0; i <= 3; i++) {
156*4882a593Smuzhiyun 		rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
157*4882a593Smuzhiyun 		time = time >> 8;
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* Start clock */
161*4882a593Smuzhiyun 	rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun  * Reset the RTC. We setting the date back to 1970-01-01.
168*4882a593Smuzhiyun  * We also enable the oscillator output on the SQW/OUT pin and program
169*4882a593Smuzhiyun  * it for 32,768 Hz output. Note that according to the datasheet, turning
170*4882a593Smuzhiyun  * on the square wave output increases the current drain on the backup
171*4882a593Smuzhiyun  * battery to something between 480nA and 800nA.
172*4882a593Smuzhiyun  */
rtc_reset(void)173*4882a593Smuzhiyun void rtc_reset (void){
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	struct rtc_time tmp;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* clear status flags */
178*4882a593Smuzhiyun 	rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/* Initialise DS1374 oriented to MPC8349E-ADS */
181*4882a593Smuzhiyun 	rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
182*4882a593Smuzhiyun 				 |RTC_CTL_BIT_WACE
183*4882a593Smuzhiyun 				 |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
184*4882a593Smuzhiyun 							      - set to 0 */
185*4882a593Smuzhiyun 	rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
186*4882a593Smuzhiyun 				|RTC_CTL_BIT_WDSTR
187*4882a593Smuzhiyun 				|RTC_CTL_BIT_RS1
188*4882a593Smuzhiyun 				|RTC_CTL_BIT_RS2
189*4882a593Smuzhiyun 				|RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
190*4882a593Smuzhiyun 							      set BBSQW and SQW to 32k
191*4882a593Smuzhiyun 							      - set to 1 */
192*4882a593Smuzhiyun 	tmp.tm_year = 1970;
193*4882a593Smuzhiyun 	tmp.tm_mon = 1;
194*4882a593Smuzhiyun 	tmp.tm_mday= 1;
195*4882a593Smuzhiyun 	tmp.tm_hour = 0;
196*4882a593Smuzhiyun 	tmp.tm_min = 0;
197*4882a593Smuzhiyun 	tmp.tm_sec = 0;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	rtc_set(&tmp);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	printf("RTC:   %4d-%02d-%02d %2d:%02d:%02d UTC\n",
202*4882a593Smuzhiyun 		tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
203*4882a593Smuzhiyun 		tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
206*4882a593Smuzhiyun 	rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
207*4882a593Smuzhiyun 	rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun /*
211*4882a593Smuzhiyun  * Helper functions
212*4882a593Smuzhiyun  */
rtc_read(uchar reg)213*4882a593Smuzhiyun static uchar rtc_read (uchar reg)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
rtc_write(uchar reg,uchar val,bool set)218*4882a593Smuzhiyun static void rtc_write(uchar reg, uchar val, bool set)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	if (set == true) {
221*4882a593Smuzhiyun 		val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
222*4882a593Smuzhiyun 		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
223*4882a593Smuzhiyun 	} else {
224*4882a593Smuzhiyun 		val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
225*4882a593Smuzhiyun 		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
rtc_write_raw(uchar reg,uchar val)229*4882a593Smuzhiyun static void rtc_write_raw (uchar reg, uchar val)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 		i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun #endif
234