1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2001-2008
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun * Keith Outwater, keith_outwater@mvis.com`
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
11*4882a593Smuzhiyun * DS1337 Real Time Clock (RTC).
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <command.h>
16*4882a593Smuzhiyun #include <rtc.h>
17*4882a593Smuzhiyun #include <i2c.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * RTC register addresses
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun #if defined CONFIG_RTC_DS1337
25*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x0
26*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x1
27*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x2
28*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x3
29*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x4
30*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x5
31*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x6
32*4882a593Smuzhiyun #define RTC_CTL_REG_ADDR 0x0e
33*4882a593Smuzhiyun #define RTC_STAT_REG_ADDR 0x0f
34*4882a593Smuzhiyun #define RTC_TC_REG_ADDR 0x10
35*4882a593Smuzhiyun #elif defined CONFIG_RTC_DS1388
36*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x1
37*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x2
38*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x3
39*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x4
40*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x5
41*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x6
42*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x7
43*4882a593Smuzhiyun #define RTC_CTL_REG_ADDR 0x0c
44*4882a593Smuzhiyun #define RTC_STAT_REG_ADDR 0x0b
45*4882a593Smuzhiyun #define RTC_TC_REG_ADDR 0x0a
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * RTC control register bits
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
52*4882a593Smuzhiyun #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
53*4882a593Smuzhiyun #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
54*4882a593Smuzhiyun #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
55*4882a593Smuzhiyun #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
56*4882a593Smuzhiyun #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * RTC status register bits
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
62*4882a593Smuzhiyun #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
63*4882a593Smuzhiyun #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
67*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * Get the current time from the RTC
71*4882a593Smuzhiyun */
rtc_get(struct rtc_time * tmp)72*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun int rel = 0;
75*4882a593Smuzhiyun uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun control = rtc_read (RTC_CTL_REG_ADDR);
78*4882a593Smuzhiyun status = rtc_read (RTC_STAT_REG_ADDR);
79*4882a593Smuzhiyun sec = rtc_read (RTC_SEC_REG_ADDR);
80*4882a593Smuzhiyun min = rtc_read (RTC_MIN_REG_ADDR);
81*4882a593Smuzhiyun hour = rtc_read (RTC_HR_REG_ADDR);
82*4882a593Smuzhiyun wday = rtc_read (RTC_DAY_REG_ADDR);
83*4882a593Smuzhiyun mday = rtc_read (RTC_DATE_REG_ADDR);
84*4882a593Smuzhiyun mon_cent = rtc_read (RTC_MON_REG_ADDR);
85*4882a593Smuzhiyun year = rtc_read (RTC_YR_REG_ADDR);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* No century bit, assume year 2000 */
88*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1388
89*4882a593Smuzhiyun mon_cent |= 0x80;
90*4882a593Smuzhiyun #endif
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
93*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
94*4882a593Smuzhiyun year, mon_cent, mday, wday, hour, min, sec, control, status);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (status & RTC_STAT_BIT_OSF) {
97*4882a593Smuzhiyun printf ("### Warning: RTC oscillator has stopped\n");
98*4882a593Smuzhiyun /* clear the OSF flag */
99*4882a593Smuzhiyun rtc_write (RTC_STAT_REG_ADDR,
100*4882a593Smuzhiyun rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
101*4882a593Smuzhiyun rel = -1;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun tmp->tm_sec = bcd2bin (sec & 0x7F);
105*4882a593Smuzhiyun tmp->tm_min = bcd2bin (min & 0x7F);
106*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x3F);
107*4882a593Smuzhiyun tmp->tm_mday = bcd2bin (mday & 0x3F);
108*4882a593Smuzhiyun tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
109*4882a593Smuzhiyun tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
110*4882a593Smuzhiyun tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
111*4882a593Smuzhiyun tmp->tm_yday = 0;
112*4882a593Smuzhiyun tmp->tm_isdst= 0;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
115*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
116*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return rel;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /*
123*4882a593Smuzhiyun * Set the RTC
124*4882a593Smuzhiyun */
rtc_set(struct rtc_time * tmp)125*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun uchar century;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
130*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
131*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun century = (tmp->tm_year >= 2000) ? 0x80 : 0;
136*4882a593Smuzhiyun rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
139*4882a593Smuzhiyun rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
140*4882a593Smuzhiyun rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
141*4882a593Smuzhiyun rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
142*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /*
149*4882a593Smuzhiyun * Reset the RTC. We also enable the oscillator output on the
150*4882a593Smuzhiyun * SQW/INTB* pin and program it for 32,768 Hz output. Note that
151*4882a593Smuzhiyun * according to the datasheet, turning on the square wave output
152*4882a593Smuzhiyun * increases the current drain on the backup battery from about
153*4882a593Smuzhiyun * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
154*4882a593Smuzhiyun * off the OSC output.
155*4882a593Smuzhiyun */
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1337_NOOSC
158*4882a593Smuzhiyun #define RTC_DS1337_RESET_VAL \
159*4882a593Smuzhiyun (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
160*4882a593Smuzhiyun #else
161*4882a593Smuzhiyun #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
162*4882a593Smuzhiyun #endif
rtc_reset(void)163*4882a593Smuzhiyun void rtc_reset (void)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1337
166*4882a593Smuzhiyun rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
167*4882a593Smuzhiyun #elif defined CONFIG_RTC_DS1388
168*4882a593Smuzhiyun rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
169*4882a593Smuzhiyun #endif
170*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1339_TCR_VAL
171*4882a593Smuzhiyun rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
172*4882a593Smuzhiyun #endif
173*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1388_TCR_VAL
174*4882a593Smuzhiyun rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
175*4882a593Smuzhiyun #endif
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * Helper functions
181*4882a593Smuzhiyun */
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static
rtc_read(uchar reg)184*4882a593Smuzhiyun uchar rtc_read (uchar reg)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun
rtc_write(uchar reg,uchar val)190*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #endif
196