1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2001, 2002, 2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun * Keith Outwater, keith_outwater@mvis.com`
5*4882a593Smuzhiyun * Steven Scholz, steven.scholz@imc-berlin.de
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
12*4882a593Smuzhiyun * DS1307 and DS1338/9 Real Time Clock (RTC).
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * based on ds1337.c
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <command.h>
19*4882a593Smuzhiyun #include <dm.h>
20*4882a593Smuzhiyun #include <rtc.h>
21*4882a593Smuzhiyun #include <i2c.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun enum ds_type {
24*4882a593Smuzhiyun ds_1307,
25*4882a593Smuzhiyun ds_1337,
26*4882a593Smuzhiyun ds_1340,
27*4882a593Smuzhiyun mcp794xx,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * RTC register addresses
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun #define RTC_SEC_REG_ADDR 0x00
34*4882a593Smuzhiyun #define RTC_MIN_REG_ADDR 0x01
35*4882a593Smuzhiyun #define RTC_HR_REG_ADDR 0x02
36*4882a593Smuzhiyun #define RTC_DAY_REG_ADDR 0x03
37*4882a593Smuzhiyun #define RTC_DATE_REG_ADDR 0x04
38*4882a593Smuzhiyun #define RTC_MON_REG_ADDR 0x05
39*4882a593Smuzhiyun #define RTC_YR_REG_ADDR 0x06
40*4882a593Smuzhiyun #define RTC_CTL_REG_ADDR 0x07
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
45*4882a593Smuzhiyun #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
46*4882a593Smuzhiyun #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
47*4882a593Smuzhiyun #define RTC_CTL_BIT_OUT 0x80 /* Output Control */
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* MCP7941X-specific bits */
50*4882a593Smuzhiyun #define MCP7941X_BIT_ST 0x80
51*4882a593Smuzhiyun #define MCP7941X_BIT_VBATEN 0x08
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #ifndef CONFIG_DM_RTC
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
58*4882a593Smuzhiyun #undef DEBUG_RTC
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifdef DEBUG_RTC
61*4882a593Smuzhiyun #define DEBUGR(fmt, args...) printf(fmt, ##args)
62*4882a593Smuzhiyun #else
63*4882a593Smuzhiyun #define DEBUGR(fmt, args...)
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun /*---------------------------------------------------------------------*/
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifndef CONFIG_SYS_I2C_RTC_ADDR
68*4882a593Smuzhiyun # define CONFIG_SYS_I2C_RTC_ADDR 0x68
69*4882a593Smuzhiyun #endif
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
72*4882a593Smuzhiyun # error The DS1307 is specified only up to 100kHz!
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static uchar rtc_read (uchar reg);
76*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * Get the current time from the RTC
80*4882a593Smuzhiyun */
rtc_get(struct rtc_time * tmp)81*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int rel = 0;
84*4882a593Smuzhiyun uchar sec, min, hour, mday, wday, mon, year;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #ifdef CONFIG_RTC_MCP79411
87*4882a593Smuzhiyun read_rtc:
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun sec = rtc_read (RTC_SEC_REG_ADDR);
90*4882a593Smuzhiyun min = rtc_read (RTC_MIN_REG_ADDR);
91*4882a593Smuzhiyun hour = rtc_read (RTC_HR_REG_ADDR);
92*4882a593Smuzhiyun wday = rtc_read (RTC_DAY_REG_ADDR);
93*4882a593Smuzhiyun mday = rtc_read (RTC_DATE_REG_ADDR);
94*4882a593Smuzhiyun mon = rtc_read (RTC_MON_REG_ADDR);
95*4882a593Smuzhiyun year = rtc_read (RTC_YR_REG_ADDR);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
98*4882a593Smuzhiyun "hr: %02x min: %02x sec: %02x\n",
99*4882a593Smuzhiyun year, mon, mday, wday, hour, min, sec);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #ifdef CONFIG_RTC_DS1307
102*4882a593Smuzhiyun if (sec & RTC_SEC_BIT_CH) {
103*4882a593Smuzhiyun printf ("### Warning: RTC oscillator has stopped\n");
104*4882a593Smuzhiyun /* clear the CH flag */
105*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR,
106*4882a593Smuzhiyun rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
107*4882a593Smuzhiyun rel = -1;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun #endif
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #ifdef CONFIG_RTC_MCP79411
112*4882a593Smuzhiyun /* make sure that the backup battery is enabled */
113*4882a593Smuzhiyun if (!(wday & MCP7941X_BIT_VBATEN)) {
114*4882a593Smuzhiyun rtc_write(RTC_DAY_REG_ADDR,
115*4882a593Smuzhiyun wday | MCP7941X_BIT_VBATEN);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* clock halted? turn it on, so clock can tick. */
119*4882a593Smuzhiyun if (!(sec & MCP7941X_BIT_ST)) {
120*4882a593Smuzhiyun rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
121*4882a593Smuzhiyun printf("Started RTC\n");
122*4882a593Smuzhiyun goto read_rtc;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun tmp->tm_sec = bcd2bin (sec & 0x7F);
128*4882a593Smuzhiyun tmp->tm_min = bcd2bin (min & 0x7F);
129*4882a593Smuzhiyun tmp->tm_hour = bcd2bin (hour & 0x3F);
130*4882a593Smuzhiyun tmp->tm_mday = bcd2bin (mday & 0x3F);
131*4882a593Smuzhiyun tmp->tm_mon = bcd2bin (mon & 0x1F);
132*4882a593Smuzhiyun tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
133*4882a593Smuzhiyun tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
134*4882a593Smuzhiyun tmp->tm_yday = 0;
135*4882a593Smuzhiyun tmp->tm_isdst= 0;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
138*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
139*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return rel;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /*
146*4882a593Smuzhiyun * Set the RTC
147*4882a593Smuzhiyun */
rtc_set(struct rtc_time * tmp)148*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
151*4882a593Smuzhiyun tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
152*4882a593Smuzhiyun tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
155*4882a593Smuzhiyun printf("WARNING: year should be between 1970 and 2069!\n");
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
158*4882a593Smuzhiyun rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
159*4882a593Smuzhiyun #ifdef CONFIG_RTC_MCP79411
160*4882a593Smuzhiyun rtc_write (RTC_DAY_REG_ADDR,
161*4882a593Smuzhiyun bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
162*4882a593Smuzhiyun #else
163*4882a593Smuzhiyun rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
164*4882a593Smuzhiyun #endif
165*4882a593Smuzhiyun rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
166*4882a593Smuzhiyun rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
167*4882a593Smuzhiyun rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
168*4882a593Smuzhiyun #ifdef CONFIG_RTC_MCP79411
169*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
170*4882a593Smuzhiyun #else
171*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
172*4882a593Smuzhiyun #endif
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun * Reset the RTC. We setting the date back to 1970-01-01.
180*4882a593Smuzhiyun * We also enable the oscillator output on the SQW/OUT pin and program
181*4882a593Smuzhiyun * it for 32,768 Hz output. Note that according to the datasheet, turning
182*4882a593Smuzhiyun * on the square wave output increases the current drain on the backup
183*4882a593Smuzhiyun * battery to something between 480nA and 800nA.
184*4882a593Smuzhiyun */
rtc_reset(void)185*4882a593Smuzhiyun void rtc_reset (void)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct rtc_time tmp;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
190*4882a593Smuzhiyun rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun tmp.tm_year = 1970;
193*4882a593Smuzhiyun tmp.tm_mon = 1;
194*4882a593Smuzhiyun tmp.tm_mday= 1;
195*4882a593Smuzhiyun tmp.tm_hour = 0;
196*4882a593Smuzhiyun tmp.tm_min = 0;
197*4882a593Smuzhiyun tmp.tm_sec = 0;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun rtc_set(&tmp);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
202*4882a593Smuzhiyun tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
203*4882a593Smuzhiyun tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /*
210*4882a593Smuzhiyun * Helper functions
211*4882a593Smuzhiyun */
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static
rtc_read(uchar reg)214*4882a593Smuzhiyun uchar rtc_read (uchar reg)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun
rtc_write(uchar reg,uchar val)220*4882a593Smuzhiyun static void rtc_write (uchar reg, uchar val)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun #endif /* CONFIG_CMD_DATE*/
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun #endif /* !CONFIG_DM_RTC */
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun #ifdef CONFIG_DM_RTC
ds1307_rtc_set(struct udevice * dev,const struct rtc_time * tm)230*4882a593Smuzhiyun static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun int ret;
233*4882a593Smuzhiyun uchar buf[7];
234*4882a593Smuzhiyun enum ds_type type = dev_get_driver_data(dev);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
237*4882a593Smuzhiyun tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
238*4882a593Smuzhiyun tm->tm_hour, tm->tm_min, tm->tm_sec);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (tm->tm_year < 1970 || tm->tm_year > 2069)
241*4882a593Smuzhiyun printf("WARNING: year should be between 1970 and 2069!\n");
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
244*4882a593Smuzhiyun buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
245*4882a593Smuzhiyun buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
246*4882a593Smuzhiyun buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
247*4882a593Smuzhiyun buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
248*4882a593Smuzhiyun buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
249*4882a593Smuzhiyun buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (type == mcp794xx) {
252*4882a593Smuzhiyun buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
253*4882a593Smuzhiyun buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
257*4882a593Smuzhiyun if (ret < 0)
258*4882a593Smuzhiyun return ret;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return 0;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
ds1307_rtc_get(struct udevice * dev,struct rtc_time * tm)263*4882a593Smuzhiyun static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun int ret;
266*4882a593Smuzhiyun uchar buf[7];
267*4882a593Smuzhiyun enum ds_type type = dev_get_driver_data(dev);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun read_rtc:
270*4882a593Smuzhiyun ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
271*4882a593Smuzhiyun if (ret < 0)
272*4882a593Smuzhiyun return ret;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (type == ds_1307) {
275*4882a593Smuzhiyun if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
276*4882a593Smuzhiyun printf("### Warning: RTC oscillator has stopped\n");
277*4882a593Smuzhiyun /* clear the CH flag */
278*4882a593Smuzhiyun buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
279*4882a593Smuzhiyun dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
280*4882a593Smuzhiyun buf[RTC_SEC_REG_ADDR]);
281*4882a593Smuzhiyun return -1;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (type == mcp794xx) {
286*4882a593Smuzhiyun /* make sure that the backup battery is enabled */
287*4882a593Smuzhiyun if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
288*4882a593Smuzhiyun dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR,
289*4882a593Smuzhiyun buf[RTC_DAY_REG_ADDR] |
290*4882a593Smuzhiyun MCP7941X_BIT_VBATEN);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* clock halted? turn it on, so clock can tick. */
294*4882a593Smuzhiyun if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) {
295*4882a593Smuzhiyun dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
296*4882a593Smuzhiyun MCP7941X_BIT_ST);
297*4882a593Smuzhiyun printf("Started RTC\n");
298*4882a593Smuzhiyun goto read_rtc;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
303*4882a593Smuzhiyun tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
304*4882a593Smuzhiyun tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
305*4882a593Smuzhiyun tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
306*4882a593Smuzhiyun tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
307*4882a593Smuzhiyun tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
308*4882a593Smuzhiyun (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
309*4882a593Smuzhiyun 1900 : 2000);
310*4882a593Smuzhiyun tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
311*4882a593Smuzhiyun tm->tm_yday = 0;
312*4882a593Smuzhiyun tm->tm_isdst = 0;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
315*4882a593Smuzhiyun tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
316*4882a593Smuzhiyun tm->tm_hour, tm->tm_min, tm->tm_sec);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return 0;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
ds1307_rtc_reset(struct udevice * dev)321*4882a593Smuzhiyun static int ds1307_rtc_reset(struct udevice *dev)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun int ret;
324*4882a593Smuzhiyun struct rtc_time tmp = {
325*4882a593Smuzhiyun .tm_year = 1970,
326*4882a593Smuzhiyun .tm_mon = 1,
327*4882a593Smuzhiyun .tm_mday = 1,
328*4882a593Smuzhiyun .tm_hour = 0,
329*4882a593Smuzhiyun .tm_min = 0,
330*4882a593Smuzhiyun .tm_sec = 0,
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* clear Clock Halt */
334*4882a593Smuzhiyun ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
335*4882a593Smuzhiyun if (ret < 0)
336*4882a593Smuzhiyun return ret;
337*4882a593Smuzhiyun ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
338*4882a593Smuzhiyun RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
339*4882a593Smuzhiyun RTC_CTL_BIT_RS0);
340*4882a593Smuzhiyun if (ret < 0)
341*4882a593Smuzhiyun return ret;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun ret = ds1307_rtc_set(dev, &tmp);
344*4882a593Smuzhiyun if (ret < 0)
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun debug("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
348*4882a593Smuzhiyun tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
349*4882a593Smuzhiyun tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
ds1307_probe(struct udevice * dev)354*4882a593Smuzhiyun static int ds1307_probe(struct udevice *dev)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
357*4882a593Smuzhiyun DM_I2C_CHIP_WR_ADDRESS);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return 0;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun static const struct rtc_ops ds1307_rtc_ops = {
363*4882a593Smuzhiyun .get = ds1307_rtc_get,
364*4882a593Smuzhiyun .set = ds1307_rtc_set,
365*4882a593Smuzhiyun .reset = ds1307_rtc_reset,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun static const struct udevice_id ds1307_rtc_ids[] = {
369*4882a593Smuzhiyun { .compatible = "dallas,ds1307", .data = ds_1307 },
370*4882a593Smuzhiyun { .compatible = "dallas,ds1337", .data = ds_1337 },
371*4882a593Smuzhiyun { .compatible = "dallas,ds1340", .data = ds_1340 },
372*4882a593Smuzhiyun { .compatible = "microchip,mcp7941x", .data = mcp794xx },
373*4882a593Smuzhiyun { }
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun U_BOOT_DRIVER(rtc_ds1307) = {
377*4882a593Smuzhiyun .name = "rtc-ds1307",
378*4882a593Smuzhiyun .id = UCLASS_RTC,
379*4882a593Smuzhiyun .probe = ds1307_probe,
380*4882a593Smuzhiyun .of_match = ds1307_rtc_ids,
381*4882a593Smuzhiyun .ops = &ds1307_rtc_ops,
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun #endif /* CONFIG_DM_RTC */
384