1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * Date & Time support for the internal Real-time Timer
10*4882a593Smuzhiyun * of AT91SAM9260 and compatibles.
11*4882a593Smuzhiyun * Compatible with the LinuX rtc driver workaround:
12*4882a593Smuzhiyun * The RTT cannot be written to, but only reset.
13*4882a593Smuzhiyun * The actual time is the sum of RTT and one of
14*4882a593Smuzhiyun * the four GPBR registers.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * The at91sam9260 has 4 GPBR (0-3).
17*4882a593Smuzhiyun * For their typical use see at91_gpbr.h !
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * make sure u-boot and kernel use the same GPBR !
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <common.h>
23*4882a593Smuzhiyun #include <command.h>
24*4882a593Smuzhiyun #include <rtc.h>
25*4882a593Smuzhiyun #include <asm/io.h>
26*4882a593Smuzhiyun #include <linux/errno.h>
27*4882a593Smuzhiyun #include <asm/arch/hardware.h>
28*4882a593Smuzhiyun #include <asm/arch/at91_rtt.h>
29*4882a593Smuzhiyun #include <asm/arch/at91_gpbr.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE)
32*4882a593Smuzhiyun
rtc_get(struct rtc_time * tmp)33*4882a593Smuzhiyun int rtc_get (struct rtc_time *tmp)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
36*4882a593Smuzhiyun at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
37*4882a593Smuzhiyun ulong tim;
38*4882a593Smuzhiyun ulong tim2;
39*4882a593Smuzhiyun ulong off;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun do {
42*4882a593Smuzhiyun tim = readl(&rtt->vr);
43*4882a593Smuzhiyun tim2 = readl(&rtt->vr);
44*4882a593Smuzhiyun } while (tim!=tim2);
45*4882a593Smuzhiyun off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
46*4882a593Smuzhiyun /* off==0 means time is invalid, but we ignore that */
47*4882a593Smuzhiyun rtc_to_tm(tim+off, tmp);
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
rtc_set(struct rtc_time * tmp)51*4882a593Smuzhiyun int rtc_set (struct rtc_time *tmp)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
54*4882a593Smuzhiyun at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
55*4882a593Smuzhiyun ulong tim;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun tim = rtc_mktime(tmp);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* clear alarm, set prescaler to 32768, clear counter */
60*4882a593Smuzhiyun writel(32768+AT91_RTT_RTTRST, &rtt->mr);
61*4882a593Smuzhiyun writel(~0, &rtt->ar);
62*4882a593Smuzhiyun writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
63*4882a593Smuzhiyun /* wait for counter clear to happen, takes less than a 1/32768th second */
64*4882a593Smuzhiyun while (readl(&rtt->vr) != 0)
65*4882a593Smuzhiyun ;
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
rtc_reset(void)69*4882a593Smuzhiyun void rtc_reset (void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
72*4882a593Smuzhiyun at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* clear alarm, set prescaler to 32768, clear counter */
75*4882a593Smuzhiyun writel(32768+AT91_RTT_RTTRST, &rtt->mr);
76*4882a593Smuzhiyun writel(~0, &rtt->ar);
77*4882a593Smuzhiyun writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
78*4882a593Smuzhiyun /* wait for counter clear to happen, takes less than a 1/32768th second */
79*4882a593Smuzhiyun while (readl(&rtt->vr) != 0)
80*4882a593Smuzhiyun ;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #endif
84